C8051F311-GM Silicon Laboratories Inc, C8051F311-GM Datasheet - Page 161

• Manufacturer Part Number: C8051F311-GM
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F31xr

Specifications of C8051F311-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F310DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 17 Channel
• No. Of I/o's: 25
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F31x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1446 - ADAPTER PROGRAM TOOLSTICK F311336-1253 - DEV KIT FOR C8051F310/F311
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1254

14.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the
shown response options are only the typical responses; application-specific procedures are allowed as
long as they conform to the SMBus specification. Highlighted responses are allowed but do not conform to
the SMBus specification.
1100
1000
1110
Values Read
0
0
0
1
0
0
0
0
X
X
0
1
Current SMbus State
A master START was
generated.
A master data or address byte
was transmitted; NACK
received.
A master data or address byte
was transmitted; ACK
received.
A master data byte was
received; ACK requested.
Table 14.4. SMBus Status Decoding
Rev. 1.7
C8051F310/1/2/3/4/5/6/7
Typical Response Options
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte; Read
SMB0DAT.
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
Send ACK followed by repeated
START.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
0
1
0
0
0
1
1
0
0
0
1
1
1
0
0
Written
Values
0
0
1
0
1
1
0
0
0
1
1
0
0
0
0
161
X
X
X
X
X
X
X
X
1
0
0
1
0
1
0