C8051F311-GM Silicon Laboratories Inc, C8051F311-GM Datasheet - Page 225
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C8051F311-GM
Manufacturer Part Number
C8051F311-GM
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Datasheets
1.C8051F310-TB.pdf
(228 pages)
2.C8051F311-GM.pdf
(2 pages)
3.C8051F310-GQ.pdf
(218 pages)
Specifications of C8051F311-GM
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F310DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
No. Of I/o's
25
Ram Memory Size
1280Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
24QFN EP
Device Core
8051
Family Name
C8051F31x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1446 - ADAPTER PROGRAM TOOLSTICK F311336-1253 - DEV KIT FOR C8051F310/F311
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1254
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F311-GM
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Part Number:
C8051F311-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
20.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming functions may be performed. This is possible because C2 communication is typically
performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
In this halted state, the C2 interface can safely ‘borrow’ the C2CK (/RST) and C2D (P3.0) pins. In most
applications, external resistors are required to isolate C2 interface traffic from the user application. A typi-
cal isolation configuration is shown in Figure 20.1.
The configuration in Figure 20.1 assumes the following:
Additional resistors may be necessary depending on the specific application.
1. The user input (b) cannot change state while the target device is halted.
2. The /RST pin on the target device is used as an input only.
/Reset (a)
Output (c)
Input (b)
Figure 20.1. Typical C2 Pin Sharing
C2 Interface Master
Rev. 1.7
C8051F310/1/2/3/4/5/6/7
C2CK
C2D
C8051Fxxx
225