C8051F311-GM Silicon Laboratories Inc, C8051F311-GM Datasheet - Page 71

IC 8051 MCU 16K FLASH 28MLP

C8051F311-GM

Manufacturer Part Number
C8051F311-GM
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Datasheets

Specifications of C8051F311-GM

Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F310DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
No. Of I/o's
25
Ram Memory Size
1280Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Package
24QFN EP
Device Core
8051
Family Name
C8051F31x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1446 - ADAPTER PROGRAM TOOLSTICK F311336-1253 - DEV KIT FOR C8051F310/F311
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1254

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C8051F311-GM
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The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for
n = 0 or 1). The user can program both the amount of hysteresis voltage (referred to the input voltage) and
the positive and negative-going symmetry of this hysteresis around the threshold voltage.
The Comparator hysteresis is programmed using Bits3-0 in the Comparator Control Register CPTnCN
(shown in SFR Definition 7.1 and SFR Definition 7.4). The amount of negative hysteresis voltage is
determined by the settings of the CPnHYN bits. As shown in Table 7.1, settings of 20, 10 or 5 mV of
negative hysteresis can be programmed, or negative hysteresis can be disabled. In a similar way, the
amount of positive hysteresis is determined by the setting the CPnHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. (For Inter-
rupt enable and priority control, see
to logic 1 upon a Comparator falling-edge interrupt, and the CPnRIF flag is set to logic 1 upon the Compar-
ator rising-edge interrupt. Once set, these bits remain set until cleared by software. The output state of the
Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by set-
ting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Compar-
ator is enabled by setting the CPnEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered-on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed. This Power Up Time is specified in Table 7.1 on page 78.
(Programmed with CP0HYP Bits)
INPUTS
Positive Hysteresis Voltage
OUTPUT
VIN+
VIN-
CIRCUIT CONFIGURATION
Figure 7.3. Comparator Hysteresis Plot
Positive Hysteresis
CP0+
CP0-
VIN+
VIN-
Disabled
V
OL
Section “8.3. Interrupt Handler” on page
V
OH
+
_
CP0
Positive Hysteresis
Maximum
Rev. 1.7
OUT
Negative Hysteresis
C8051F310/1/2/3/4/5/6/7
Disabled
Negative Hysteresis
(Programmed by CP0HYN Bits)
Maximum
Negative Hysteresis Voltage
93). The CPnFIF flag is set
71

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