MCF52213CAE50 Freescale Semiconductor, MCF52213CAE50 Datasheet - Page 23
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MCF52213CAE50
Manufacturer Part Number
MCF52213CAE50
Description
IC MCU 32BIT 128K FLASH 64-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5221xr
Datasheet
1.MCF52213CAE50.pdf
(56 pages)
Specifications of MCF52213CAE50
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART, USB OTG
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
MCF522x
Core
ColdFire V2
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, QSPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
43
Number Of Timers
18
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
A/d Bit Size
12 bit
A/d Channels Available
8
Height
1.4 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
10 mm
For Use With
M52210DEMO - BOARD DEV MCF5221X LOW COST
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF52213CAE50
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.10
Table 11
1.11
Table 12
Freescale Semiconductor
Transmit Serial Data
Receive Serial Data
DMA Timer Output
Request-to-Send
DMA Timer Input
describes the UART module signals.
describes the signals of the four DMA timer modules.
Clear-to-Send
Signal Name
Signal Name
Signal Name
Serial Clock
Serial Data
UART Module Signals
DMA Timer Signals
Output
Input
Abbreviation
Abbreviation
Abbreviation
DTOUT
URXDn
UTXDn
UCTSn
URTSn
SDAn
SCLn
DTIN
MCF52211 ColdFire Microcontroller, Rev. 2
Table 11. UART Module Signals
Open-drain clock signal for the for the I
In master mode, this clock is driven by the I
is in slave mode, this clock becomes the clock input.
Open-drain signal that serves as the data input/output for the I
interface.
Event input to the DMA timer modules.
Programmable output from the DMA timer modules.
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, LSB first, on this pin at
the falling edge of the serial clock source.
Receiver serial data inputs for the UART modules. Data is received on
this pin LSB first. When the UART clock is stopped for power-down
mode, any transition on this pin restarts the clock.
Indication to the UART modules that they can begin data
transmission.
Automatic request-to-send outputs from the UART modules. This
signal can also be configured to be asserted and negated as a
function of the RxFIFO level.
Table 12. DMA Timer Signals
Table 10. I
2
C I/O Signals
Function
Function
Function
2
C interface. When the bus is
2
C module; when the bus
Family Configurations
2
C
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
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