M30622SAFP#U5 Renesas Electronics America, M30622SAFP#U5 Datasheet - Page 308

• Manufacturer Part Number: M30622SAFP#U5
• Description: IC M16C MPU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30622SAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Timing
Switching characteristics (referenced to V
85
Table 1.31.22. Memory expansion and microprocessor modes
Note 1: Calculated according to the BCLK frequency as follows:
Note 2: This is standard value shows the timing when the output is off,
Note 3: Specify a product of –40°C to 85°C to use it.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
d(BCLK-CS)
h(BCLK-CS)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
h(RD-AD)
h(WR-AD)
d(DB-WR)
h(WR-DB)
d(BCLK-ALE)
h(BCLK-ALE)
Symbol
o
C (Note 3), CM15 = “1” unless otherwise specified)
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
by a circuit of the right figure.
For example, when V
of output “L” level is
td(DB – WR) =
Address output delay time
Address output hold time (BCLK standard)
Chip select output hold time (BCLK standard)
ALE signal output hold time
RD signal output hold time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (WR standard)(Note2)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
ALE signal output delay time
RD signal output delay time
WR signal output delay time
Data output hold time (BCLK standard)
Data output delay time (WR standard)
(when accessing external memory area with wait)
t = –CR X ln (1 – V
t = – 30pF X 1k
= 6.7ns.
f(BCLK)
Parameter
10
OL
9
= 0.2V
X ln (1 – 0.2V
OL
– 80
/ V
CC
CC
, C = 30pF, R = 1k , hold time
)
CC
[ns]
CC
= 3V, V
/ V
CC
SS
)
Measuring condition
= 0V at Topr = – 20
Figure 1.31.1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Note1)
Min.
– 4
Standard
4
0
0
4
0
0
4
0
o
C to 85
Max.
DBi
60
60
60
60
60
80
(Low voltage version)
Mitsubishi microcomputers
o
C / – 40
M16C / 62M Group
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
o
C to
C
R
1-287