M30622SAFP#U5 Renesas Electronics America, M30622SAFP#U5 Datasheet - Page 387

• Manufacturer Part Number: M30622SAFP#U5
• Description: IC M16C MPU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30622SAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Clock-Synchronous Serial I/O
2-68
Operation (1) Writing dummy data to the UARTi transmit buffer register, setting the receive enable bit to “1”,
2.4.4 Operation of Serial I/O (reception in clock-synchronous serial I/O mode)
In receiving data in clock-synchronous serial I/O mode, choose functions from those listed in Table 2.4.3.
Operations of the circled items are described below. Figure 2.4.13 shows the operation timing, and Fig-
ures 2.4.14 and 2.4.15 show the set-up procedures.
Table 2.4.3. Choosed functions
(2) In synchronization with the first rising edge of the transfer clock, the input signal to the RxDi
(3) When 1-byte data lines up in the UARTi receive register, the content of the UARTi receive
(4) The receive complete flag goes to “0” when the lower-order byte of the UARTi buffer register
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
Note 2: UART2 only.
Transfer clock
source
Transfer clock
RTS function
CLK polarity
and the transmit enable bit to “1”, makes the data receivable status ready. At this time, the
output from the RTSi pin goes to “L” level, which informs the transmission side that the data
receivable status is ready (output the transfer clock from the IC on the transmission side after
checking that the RTS output has gone to “L” level).
pin is stored in the highest bit of the UARTi receive register. Then, data is taken in by shifting
right the content of the UARTi reception data in synchronization with the rising edges of the
transfer clock.
register is transmitted to the UARTi receive buffer register. The transfer clock stops at “H”
level. At this time, the receive complete flag and the UARTi receive interrupt request bit goes
to “1”.
is read.
selected, UART1 CTS/RTS function can not be utilized. Set the UART1 CTS/RTS disable bit to “1”.
Item
________
O
O
O
O
_______
_______ _______
External clock (CLKi pin)
RTS function disabled
LSB first
MSB first
Internal clock (f
RTS function enabled
Input reception data at
the rising edge of the
transfer clock
Input reception data at
the falling edge of the
transfer clock
Set-up
1
/ f
8
/ f
32
)
Continuous receive
mode
Output transfer clock
to multiple pins
(Note 1)
Data logic select
function
(Note 2)
T
polarity reverse bit
(Note 2)
X
D, R
X
Item
D I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
_______ _______
O
O
O
O
Disabled
Enabled
Not selected
No reverse
No reverse
Selected
Reverse
Reverse
M16C / 62A Group
Mitsubishi microcomputers
Set-up