M30622SAFP#U5 Renesas Electronics America, M30622SAFP#U5 Datasheet - Page 416

• Manufacturer Part Number: M30622SAFP#U5
• Description: IC M16C MPU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30622SAFP#U5

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

UART
Figure 2.5.17. Operation timing of reception in UART mode (used for SIM interface)
Transfer clock
Receive enable
bit
R
T
Signal line level
(Note)
Receive
complete flag
Receive interrupt
request bit
X
X
(RE)
D
Example of wiring
Example of operation (when direct format)
D
2
2
(Note)
(Note)
(IR)
Note: TxD
(RI)
become the same signal from the logical standpoint, but the output signals turn complex, so they are shown separately. Also,
the signal level resulting from connecting TxD
“1”
“0”
“1”
“0”
“1”
“0”
The above timing applies to the following settings :
2
Shown in ( ) are bit symbols.
(1) Reception enabled
and RxD
• Parity is enabled.
• One stop bit.
• Transmit interrupt cause select bit = “1”.
Microcomputer
(2) Start reception
2
ST
ST
Start
are connected in the manner of wired OR as shown in the connection diagram. So TxD
bit
D
D
0
0
D
D
1
1
Tc
RxD
TxD
D
D
2
2
D
D
3
3
D
D
2
2
4
4
D
D
5
5
D
D
2
6
6
Cleared to “0” when interrupt request is accepted, or cleared by software
and RxD
D
D
Parity
7
7
bit
P
P
(3) Receiving is completed
2
SP
SP
Tc = 16 (n + 1) / fi
is shown as a signal line level.
Stop
bit
(4) Data is read
Read to receive buffer
fi : frequency of BRG2 count source (f
n : value set to BRG2
ST
ST
Since a parity error occurred, the
“L” level returns from TxD
D
D
0
0
D
D
1
1
D
D
SIM card
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2
2
D
D
3
3
D
D
4
4
D
D
5
5
2
D
D
1
6
6
, f
2
D
D
8
, f
and RxD
7
7
32
P
P
)
(5) Parity error occurred
M16C / 62A Group
Read to receive buffer
SP
SP
Mitsubishi microcomputers
2
ought to
2-97