HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 128

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 Instruction Set
2.5
The tables here can be used to calculate the number of states required for instruction execution.
Table 2-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation).
Table 2-4 indicates the number of cycles of each type occurring in each instruction. The total
number of states required for execution of an instruction can be calculated from these two tables as
follows:
Execution states = I
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
1. BSET #0, @FF00
2. JSR @@ 30
Rev. 2.00 Dec 27, 2004 page 114 of 128
REJ09B0214-0200
From table 2-4:
I = L = 2, J = K = M = N= 0
From table 2-3:
S
Number of states required for execution = 2
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM,
and on-chip RAM is used for stack area.
From table 2-4:
I = 2, J = K = 1, L = M = N = 0
From table 2-3:
S
Number of states required for execution = 2
I
I
= 2, S
= S
Number of Execution States
J
= S
L
= 2
K
= 2
S
I
+ J
S
J
+ K
S
K
+ L
S
2 + 2
2 + 1
L
+ M
2 = 8
2 + 1
S
M
+ N
2 = 8
S
N