HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 141

• Manufacturer Part Number: HD64F38024DV
• Description: IC H8/SLP MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300L SLPr

Specifications of HD64F38024DV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SCI
• Peripherals: LCD, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CPU operation is synchronized by a clock f). The period from the rising edge of to the next
rising edge is called one state. A memory cycle or bus cycle consists of two or three states.
For details on access to on-chip memory and to on-chip peripheral modules see the applicable
hardware manual.
4.1
Two-state access is employed for high-speed access to on-chip memory. The data bus width is 16
bits, allowing access in byte or word size. Figure 4-1 shows the on-chip memory access cycle.
On-chip Memory (RAM, ROM)
Note:
Internal address bus
Internal read signal
Internal data bus*
(read access)
Internal write signal
Internal data bus*
(write access)
Section 4 Basic Operation Timing
A 16-bit data bus is used making possible access to word-size
data in 2 states.
Figure 4-1 On-Chip Memory Access Cycle
T
1
state
Bus cycle
Address
Rev. 2.00 Dec 27, 2004 page 127 of 128
Read data
Write data
T
2
Section 4 Basic Operation Timing
state
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