HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 67

IC H8/SLP MCU FLASH 80QFP

HD64F38024DV

Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets

Specifications of HD64F38024DV

Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
* Register direct, register indirect, or absolute addressing.
2.2.15
Operation
¬ (<Bit No.> of <EAd>)
Assembly-Language Format
BNOT #xx:3, <EAd>
BNOT Rn, <EAd>
Operand Size
Byte
Description
This instruction inverts a specified bit in a general register or memory location. The bit number is
specified by 3-bit immediate data, or by the lower three-bits of a general register.
The operation is shown schematically below.
The bit is not tested before being inverted. The condition code flags are not altered.
Instruction Formats and Number of Execution States
Register direct
Register indirect
Absolute address
Register direct
Register indirect
Absolute address
<EAd>*
(<Bit No.> of <EAd>)
Addressing
mode
BNOT (bit NOT)
Byte data in register or memory
Mnem.
BNOT
BNOT
BNOT
BNOT
BNOT
BNOT
#xx:3, Rd
#xx:3,@Rd
#xx:3,@aa:8
Rn, Rd
Rn, @Rd
Rn, @aa:8
Operands
Condition Code
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Previous value remains unchanged.
Z: Previous value remains unchanged.
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Bit No.
1st byte
7
7
7
6
7
7
1
D
F
1
D
F
— — — — — — — —
#xx:3 or Rn
I
7
0 IM M
0
0
rn
2nd byte
Instruction code
rd
rd
abs
abs
Rev. 2.00 Dec 27, 2004 page 53 of 128
H
0
rd
0
Invert
rd
3rd byte
7
6
7
6
N
1
1
1
1
0
Section 2 Instruction Set
Z
0 IM M
0 IM M
V
rn
rn
4th byte
REJ09B0214-0200
C
0
0
0
0
No. of
states
BNOT
2
8
8
2
8
8

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