DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 105
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122201/df2338vfc25v_sml.jpg)
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 105 of 1246
- Download datasheet (7Mb)
3.2.2
Bit 7—Reserved: Only 0 should be written to this bit.
Bit 6—Reserved: This bit is always read as 0, and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
INTM1
0
1
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.
Bit 3
NMIEG
0
1
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output.
Bit 2
LWROD
0
1
Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ
IRQ
Bit
Initial value :
R/W
4
to IRQ
System Control Register (SYSCR)
Bit 4
INTM0
1
1
Description
Description
0
0
An interrupt is requested at the falling edge of NMI input
An interrupt is requested at the rising edge of NMI input
PF
PF
7
input is always performed from one of the ports.
:
:
3
3
is designated as LWR output pin
is designated as I/O port, and does not function as LWR output pin
R/W
—
7
0
Interrupt Control
Mode
—
—
0
2
—
—
6
0
INTM1
R/W
5
0
Description
Control of interrupts by I bit
Setting prohibited
Control of interrupts by I2 to I0 bits and IPR
Setting prohibited
INTM0
R/W
0
4
Rev.4.00 Sep. 07, 2007 Page 73 of 1210
NMIEG
R/W
3
0
LWROD IRQPAS
R/W
2
0
REJ09B0245-0400
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
4
to IRQ
RAME
R/W
0
1
7
.
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