DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 759
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122201/df2338vfc25v_sml.jpg)
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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17.3
The D/A converter includes D/A conversion circuits for two channels, each of which can operate
independently.
D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1
is written to, the new data is immediately converted. The conversion result is output by setting the
corresponding DAOE0 or DAOE1 bit to 1.
The operation example described in this section concerns D/A conversion on channel 0. Figure
17.2 shows the timing of this operation.
[1] Write the conversion data to DADR0.
[2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started and the DA0 pin becomes an
[3] If DADR0 is written to again, the new data is immediately converted. The new conversion
[4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin.
output pin. The conversion result is output after the conversion time has elapsed. The output
value is expressed by the following formula:
The conversion results are output continuously until DADR0 is written to again or the DAOE0
bit is cleared to 0.
result is output after the conversion time has elapsed.
DADR contents
Operation
256
×
V
ref
Rev.4.00 Sep. 07, 2007 Page 727 of 1210
REJ09B0245-0400
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