DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 835
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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19.14.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR1 and EBR2 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled, a
read will return H'00 and writes are invalid.
The flash memory block configuration is shown in table 19.28.
19.14.4 Erase Block Registers 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR2 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR2 and EBR1 together (setting more than one bit
will automatically clear all EBR1 and EBR2 bits to 0). Bits 7 to 4 are reserved; they are always
read as 0 and cannot be modified. When on-chip flash memory is disabled, a read will return H'00,
and writes are invalid.
The flash memory block configuration is shown in table 19.28.
Bit
EBR1
Initial value :
R/W
Bit
EBR2
Initial value :
R/W
:
:
:
:
R/W
EB7
—
—
7
0
7
0
EB6
R/W
—
—
6
0
6
0
EB5
R/W
—
—
5
0
5
0
R/W
EB4
—
—
0
0
4
4
Rev.4.00 Sep. 07, 2007 Page 803 of 1210
EB11
R/W
R/W
EB3
3
0
3
0
EB10
EB2
R/W
R/W
2
0
2
0
REJ09B0245-0400
R/W
EB1
R/W
EB9
1
0
1
0
R/W
R/W
EB0
EB8
0
0
0
0
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