R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1067

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

This LSI has a two-channel I
The I
interface functions. The register configuration that controls the I
Philips configuration, however.
Figure 21.1 shows the block diagram of the I
Figure 21.2 shows an example of I/O pin connections to external circuits.
21.1
• Continuous transmission/reception
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Six interrupt sources
• Direct bus drive
• Module stop state can be set.
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission or reception is not yet possible, drive the SCL signal low until
preparations are completed
Transmit-data-empty (including slave-address match), transmit-end, receive-data-full
(including slave-address match), arbitration lost, NACK detection, and stop condition
detection
Two pins, the SCL and SDA pins function as NMOS open-drain outputs.
2
C bus interface conforms to and provides a subset of the Philips I
Features
Section 21 I
2
C bus interface.
2
C Bus Interface 2 (IIC2)
2
C bus interface 2.
Rev. 2.00 Sep. 24, 2008 Page 1033 of 1468
2
C bus differs partly from the
Section 21 I
2
C bus (inter-IC bus)
2
C Bus Interface 2 (IIC2)
REJ09B0412-0200