R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 27

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.11 CRC Operation Circuit ..................................................................................................... 958
Section 20 USB Function Module (USB)..........................................................965
20.1
20.2
20.3
19.10.4 Receive Error Flags and Transmit Operations
19.10.5 Relation between Writing to TDR and TDRE Flag .......................................... 954
19.10.6 Restrictions on Using DTC or DMAC.............................................................. 954
19.10.7 SCI Operations during Power-Down State ....................................................... 955
19.11.1 Features............................................................................................................. 958
19.11.2 Register Descriptions ........................................................................................ 959
19.11.3 CRC Operation Circuit Operation..................................................................... 961
19.11.4 Note on CRC Operation Circuit........................................................................ 964
Features............................................................................................................................. 965
Input/Output Pins.............................................................................................................. 966
Register Descriptions........................................................................................................ 967
20.3.1
20.3.2
20.3.3
20.3.4
20.3.5
20.3.6
20.3.7
20.3.8
20.3.9
20.3.10 EP0i Data Register (EPDR0i) ........................................................................... 978
20.3.11 EP0o Data Register (EPDR0o) ......................................................................... 979
20.3.12 EP0s Data Register (EPDR0s) .......................................................................... 979
20.3.13 EP1 Data Register (EPDR1) ............................................................................. 980
20.3.14 EP2 Data Register (EPDR2) ............................................................................. 980
20.3.15 EP3 Data Register (EPDR3) ............................................................................. 981
20.3.16 EP0o Receive Data Size Register (EPSZ0o) .................................................... 981
20.3.17 EP1 Receive Data Size Register (EPSZ1) ........................................................ 982
20.3.18 Trigger Register (TRG)..................................................................................... 982
20.3.19 Data Status Register (DASTS).......................................................................... 984
20.3.20 FIFO Clear Register (FCLR) ............................................................................ 985
20.3.21 DMA Transfer Setting Register (DMA) ........................................................... 986
20.3.22 Endpoint Stall Register (EPSTL)...................................................................... 989
20.3.23 Configuration Value Register (CVR) ............................................................... 990
20.3.24 Control Register (CTLR) .................................................................................. 990
20.3.25 Endpoint Information Register (EPIR) ............................................................. 992
(Clocked Synchronous Mode Only) ................................................................. 953
Interrupt Flag Register 0 (IFR0) ....................................................................... 968
Interrupt Flag Register 1 (IFR1) ....................................................................... 970
Interrupt Flag Register 2 (IFR2) ....................................................................... 971
Interrupt Select Register 0 (ISR0)..................................................................... 973
Interrupt Select Register 1 (ISR1)..................................................................... 974
Interrupt Select Register 2 (ISR2)..................................................................... 975
Interrupt Enable Register 0 (IER0) ................................................................... 976
Interrupt Enable Register 1 (IER1) ................................................................... 977
Interrupt Enable Register 2 (IER2) ................................................................... 977
Rev. 2.00 Sep. 24, 2008 Page xxv of xxxii