R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1303

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

28.8.3
In deep software standby mode, the ports retain the states that were held during software standby
mode. The internal of the LSI is initialized by an internal reset caused by deep software standby
mode, and the reset exception handling starts as soon as deep software standby mode is canceled.
The following shows the port states at this time.
(1)
Pins for the address bus, bus control signals (CS0, AS, HWR, and LWR), and data bus operate
depending on the CPU.
(2)
Whether the ports are initialized or retain the states that were held during software standby mode
can be selected by the IOKEEP bit.
• When IOKEEP = 0
• When IOKEEP = 1
The IOKEEP bit is not initialized by an internal reset caused by canceling deep software standby
mode.
Ports are initialized by an internal reset caused by deep software standby mode.
The port states that were held in deep software standby mode are retained regardless of the LSI
internal state though the internal of the LSI is initialized by an internal reset caused by deep
software standby mode. At this time, the port states that were held in software standby mode
are retained even if settings of I/O ports or peripheral modules are set. Subsequently, the
retained port states are released when the IOKEEP bit is cleared to 0 and operation is
performed according to the internal settings.
Pins for address bus, bus control and data bus
Pins other than address bus, bus control and data bus pins
Pin State on Exit from Deep Software Standby Mode
Rev. 2.00 Sep. 24, 2008 Page 1269 of 1468
Section 28 Power-Down Modes
REJ09B0412-0200