R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 361

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
9.11.13 Refresh Control
This LSI includes a DRAM refresh control function. The refresh method is the auto-refresh. Self-
refresh cycles can be performed in software standby mode.
The refresh control function is enabled when area 2 is specified as the SDRAM space by the
DRAME and DTYPE bits in DRAMCR.
(1)
Auto-Refresh Mode
Set the RFSHE bit in REFCR to 1 to select auto-refreshing.
An auto-refresh cycle is performed when the value set in RTCOR matches the RTCNT value
(compare match). RTCNT is an up-counter operated on the input clock specified bits RTCK2 to
RTCK0 in REFCR. RTCNT is initialized upon the compare match and restarts to count up with
H'00. Accordingly, an auto-refresh cycle is repeated at intervals specified by bits RTCK2 to
RTCK0 in RTCOR. Set the bits so that the required refresh intervals of the DRAM must be
satisfied.
Since setting bits RTCK2 to RTCK0 starts RTCNT to count up, set RTCNT and RTCOR before
setting bits RTCK2 to RTCK0. When changing RTCNT and RTCOR, the count operation should
be halted. When changing bits RTCK2 to RTCK0, change them only after disabling the external
access and external bus release by the EXDMAC, if the write data buffer function is in use,
disabling the write data buffer function and reading the external space.
The external space cannot be accessed during auto-refresh.
Figure 9.76 shows auto-refresh cycle timing.
The operation of refresh counter is same as that for the DRAM interface. For details, see section
9.10.12, Refresh Control.
Rev. 2.00 Sep. 24, 2008 Page 327 of 1468
REJ09B0412-0200