R5F61668RN50FPV Renesas Electronics America, R5F61668RN50FPV Datasheet - Page 1319

• Manufacturer Part Number: R5F61668RN50FPV
• Description: IC H8SX/1668 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61668RN50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561668S000BE - KIT STARTER FOR H8SX/1668R0K561664S001BE - KIT STARTER FOR H8SX/1651HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 28 Power-Down Modes
28.12
Usage Notes
28.12.1 I/O Port Status
In software standby mode or deep software standby mode, the I/O port states are retained.
Therefore, there is no reduction in current drawn due to output currents when high-level signals
are being output.
28.12.2 Current Consumption during Oscillation Settling Standby Period
Current consumption increases during the oscillation settling standby period.
28.12.3 Module Stop State of EXDMAC, DMAC, or DTC
Depending on the operating state of the EXDMAC, DMAC, and DTC, bits MSTPA14,
MSTPA13, and MSTPA12 may not be set to 1, respectively. The module stop state setting for the
EXDMAC, DMAC, or DTC should be carried out only when the EXDMAC, DMAC, or DTC is
not activated.
For details, refer to section 10, DMA Controller (DMAC), section 11, EXDMA Controller
(EXDMAC), and section 12, Data Transfer Controller (DTC).
28.12.4 On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in a module stop state. Consequently, if the
module stop state is entered when an interrupt has been requested, it will not be possible to clear
the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be
disabled before entering a module stop state.
28.12.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC
MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU.
Rev. 2.00 Sep. 24, 2008 Page 1285 of 1468
REJ09B0412-0200