SAF-C161K-LM 3V HA Infineon Technologies, SAF-C161K-LM 3V HA Datasheet - Page 26
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SAF-C161K-LM 3V HA
Manufacturer Part Number
SAF-C161K-LM 3V HA
Description
IC MCU 16BIT ROM/LESS MQFP-80-1
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet
1.SAF-C161O-L25M_HA.pdf
(66 pages)
Specifications of SAF-C161K-LM 3V HA
Core Processor
C166
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
63
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-SQFP
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
ASC, SSC
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
63
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Packages
PG-MQFP-80
Max Clock Frequency
20.0 MHz
Sram (incl. Cache)
1.0 KByte
Program Memory
0.0 KByte
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
F161KLM3VHAXT
SAF-C161K-LM3VHA
SAF-C161K-LM3VHAINTR
SAF-C161K-LM3VHATR
SAF-C161K-LM3VHATR
SAFC161KLM3VHAXT
SP000011621
SAF-C161K-LM3VHA
SAF-C161K-LM3VHAINTR
SAF-C161K-LM3VHATR
SAF-C161K-LM3VHATR
SAFC161KLM3VHAXT
SP000011621
Instruction Set Summary
Table 5
The various addressing modes that can be used with a specific instruction, the operation
of the instructions, parameters for conditional execution of instructions, and the opcodes
for each instruction can be found in the “C166 Family Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 5
Mnemonic
ADD(B)
ADDC(B)
SUB(B)
SUBC(B)
MUL(U)
DIV(U)
DIVL(U)
CPL(B)
NEG(B)
AND(B)
OR(B)
XOR(B)
BCLR
BSET
BMOV(N)
BAND, BOR,
BXOR
BCMP
BFLDH/L
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
SHL / SHR
ROL / ROR
ASHR
Data Sheet
lists the instructions of the C161K/O in a condensed way.
Instruction Set Summary
Subtract word (byte) operands with Carry
Shift left/right direct word GPR
Description
Add word (byte) operands
Add word (byte) operands with Carry
Subtract word (byte) operands
(Un)Signed multiply direct GPR by direct GPR (16-16-bit) 2
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
Complement direct word (byte) GPR
Negate direct word (byte) GPR
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
Set direct bit
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Compare direct bit to direct bit
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
Compare word (byte) operands
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
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V2.0, 2001-01
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C161O
C161K