ST72F321BR9T6 STMicroelectronics, ST72F321BR9T6 Datasheet - Page 26

• Manufacturer Part Number: ST72F321BR9T6
• Description: MCU 8BIT 60KB FLASH/ROM 64-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F321BR9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 48
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Cpu Family: ST7
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 48
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3.8V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5586

ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
6.3 RESET SEQUENCE MANAGER (RSM)
6.3.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
■
■
■
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilise and ensures that recovery
has taken place from the Reset state. The shorter
or longer clock cycle delay should be selected by
option byte to correspond to the stabilization time
of the external oscillator used in the application
(see
The RESET vector fetch phase duration is 2 clock
cycles.
Figure 14. Reset Block Diagram
26/187
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (selected by
option byte)
RESET vector fetch
RESET
section 14.1 on page
Figure
13:
V
Figure
174).
DD
R
ON
14:
Filter
Figure 13. RESET Sequence Phases
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed.
For this reason, it is recommended to keep the
RESET pin in low state until programming mode is
entered, in order to avoid unwanted behavior.
6.3.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
“CONTROL
page 158
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized (see
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
GENERATOR
PULSE
Active Phase
for more details.
PIN
256 or 4096 CLOCK CYCLES
INTERNAL RESET
RESET
CHARACTERISTICS”
ON
weak pull-up resistor.
WATCHDOG RESET
LVD RESET
Figure
INTERNAL
RESET
15). This de-
VECTOR
h(RSTL)in
FETCH
on
in