C8051F705-GM Silicon Laboratories Inc, C8051F705-GM Datasheet - Page 188

IC 8051 MCU 15K FLASH 48-QFN

C8051F705-GM

Manufacturer Part Number
C8051F705-GM
Description
IC 8051 MCU 15K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Datasheets

Specifications of C8051F705-GM

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
15KB (15K x 8)
Program Memory Type
FLASH
Eeprom Size
32 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
Height
0.95 mm
Length
7 mm
Supply Voltage (max)
1.9 V, 3.6 V
Supply Voltage (min)
1.7 V, 1.8 V
Width
7 mm
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
336-1612-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F705-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
C8051F70x/71x
188
This example shows a crossbar configuration with XBR0 = 0x07 and XBR1 = 0x43.
Pin Number
Figure 28.6. Crossbar Priority Decoder in Example Configuration—3 Pins Skipped
SYSCLK
Function
These boxes represent Port pins which are assigned to a peripheral.
Pin Skip
Settings
Special
Signals
CP0A
CEX0
CEX1
CEX2
MISO
MOSI
NSS*
SCK
SDA
RX0
SCL
CP0
Port
TX0
ECI
T0
T1
0 1 2 3 4 5 6 7
0 0 1 1 0 0 0 0
P0SKIP
P0
0 1 2 3 4 5 6 7
1 0 0 0 0 0 0 0
Rev. 1.0
P1SKIP
P1
If a pin is skipped, it is not available for
assignment, and the crossbar will move
the assignment to the next available pin
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
P2SKIP
P2

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