C8051F705-GM Silicon Laboratories Inc, C8051F705-GM Datasheet - Page 9

• Manufacturer Part Number: C8051F705-GM
• Description: IC 8051 MCU 15K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F70xr

Specifications of C8051F705-GM

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Cap Sense, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 15KB (15K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 32 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: C8051F7x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 39
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F700DK
• Minimum Operating Temperature: - 40 C
• Height: 0.95 mm
• Length: 7 mm
• Supply Voltage (max): 1.9 V, 3.6 V
• Supply Voltage (min): 1.7 V, 1.8 V
• Width: 7 mm
• For Use With: 336-1635 - DEV KIT FOR C8051F700
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1612-5

C8051F70x/71x
Figure 18.3. EMIF Operating Modes ..................................................................... 117
Figure 18.4. Non-multiplexed 16-bit MOVX Timing ............................................... 120
Figure 18.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 121
Figure 18.6. Non-Multiplexed 8-Bit MOVX with Bank Select Timing ..................... 122
Figure 18.7. Multiplexed 16-bit MOVX Timing ....................................................... 123
Figure 18.8. Multiplexed 8-Bit MOVX without Bank Select Timing ........................ 124
Figure 18.9. Multiplexed 8-Bit MOVX with Bank Select Timing ............................. 125
Figure 23.1. EEPROM Block Diagram .................................................................. 155
Figure 25.1. Reset Sources ................................................................................... 163
Figure 25.2. Power-On and VDD Monitor Reset Timing ....................................... 164
Figure 27.1. Oscillator Options .............................................................................. 171
Figure 27.2. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 178
Figure 28.1. Port I/O Functional Block Diagram .................................................... 180
Figure 28.2. Port I/O Cell Block Diagram .............................................................. 181
Figure 28.3. Port I/O Overdrive Current ................................................................ 182
Figure 28.4. Crossbar Priority Decoder—Possible Pin Assignments .................... 186
Figure 28.5. Crossbar Priority Decoder in Example Configuration—
No Pins Skipped ............................................................................... 187
Figure 28.6. Crossbar Priority Decoder in Example Configuration—
3 Pins Skipped .................................................................................. 188
Figure 29.1. CRC0 Block Diagram ........................................................................ 211
Figure 30.1. SMBus Block Diagram ...................................................................... 219
Figure 30.2. Typical SMBus Configuration ............................................................ 220
Figure 30.3. SMBus Transaction ........................................................................... 221
Figure 30.4. Typical SMBus SCL Generation ........................................................ 223
Figure 30.5. Typical Master Write Sequence ........................................................ 232
Figure 30.6. Typical Master Read Sequence ........................................................ 233
Figure 30.7. Typical Slave Write Sequence .......................................................... 234
Figure 30.8. Typical Slave Read Sequence .......................................................... 235
Figure 31.1. SPI Block Diagram ............................................................................ 241
Figure 31.2. Multiple-Master Mode Connection Diagram ...................................... 243
Figure 31.3. 3-Wire Single Master and Single Slave Mode Connection Diagram . 243
Figure 31.4. 4-Wire Single Master Mode and Slave Mode Connection Diagram .. 244
Figure 31.5. Master Mode Data/Clock Timing ....................................................... 246
Figure 31.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 246
Figure 31.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 247
Figure 31.8. SPI Master Timing (CKPHA = 0) ....................................................... 251
Figure 31.9. SPI Master Timing (CKPHA = 1) ....................................................... 251
Figure 31.10. SPI Slave Timing (CKPHA = 0) ....................................................... 252
Figure 31.11. SPI Slave Timing (CKPHA = 1) ....................................................... 252
Figure 32.1. UART0 Block Diagram ...................................................................... 254
Figure 32.2. UART0 Baud Rate Logic ................................................................... 255
Figure 32.3. UART Interconnect Diagram ............................................................. 256
Figure 32.4. 8-Bit UART Timing Diagram .............................................................. 256
Figure 32.5. 9-Bit UART Timing Diagram .............................................................. 257
Rev. 1.0
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