C8051F347-GM Silicon Laboratories Inc, C8051F347-GM Datasheet - Page 144

• Manufacturer Part Number: C8051F347-GM
• Description: IC 8051 MCU 32K FLASH MEM 32-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F347-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1348-5

C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
15.1. Priority Crossbar Decoder
The Priority Crossbar Decoder (Figure 15.3) assigns a priority to each I/O function, starting at the top with
UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that
resource (excluding UART0, which is always at pins 4 and 5). If a Port pin is assigned, the Crossbar skips
that pin when assigning the next selected resource. Additionally, the Crossbar will skip Port pins whose
associated bits in the PnSKIP registers are set. The PnSKIP registers allow software to skip Port pins that
are to be used for analog input, dedicated functions, or GPIO.
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to the VREF signal, external oscillator
pins (XTAL1, XTAL2), the ADC’s external conversion start signal (CNVSTR), EMIF control signals, and any
selected ADC or Comparator inputs. The PnSKIP registers may also be used to skip pins to be used as
GPIO. The Crossbar skips selected pins as if they were already assigned, and moves to the next unas-
signed pin. Figure 15.3 shows all the possible pins available to each peripheral. Figure 15.4 shows the
Crossbar Decoder priority with no Port pins skipped. Figure 15.5 shows a Crossbar example with pins
P0.2, P0.3, and P1.0 skipped.
144
SF Signals
(32-pin
Package)
SF Signals
(48-pin
Package)
PIN I/O
TX0
RX0
SCK
MISO
MOSI
NSS*
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
ECI
T0
T1
TX1**
RX1**
SF Signals
Port pin potentially available to peripheral
Special Function Signals are not assigned by the Crossbar. When these signals are
enabled, the Crossbar must be manually configured to skip their corresponding port pins.
0
1
2
3
Figure 15.3. Peripheral Availability on Port I/O Pins
P0
4
5
6
7
0
1
2
3
P1
4
5
Rev. 1.3
6
7
0
1
2
**UART1 available only on C8051F340/1/4/5/8/A/B devices
3
P2
4
5
6
*NSS is only pinned out in 4-wire SPI mode
7
0
1
P3.1-P3.7 unavailable on
the 32-pin packages
2
3
P3
4
5
6
7