C8051F347-GM Silicon Laboratories Inc, C8051F347-GM Datasheet - Page 163

• Manufacturer Part Number: C8051F347-GM
• Description: IC 8051 MCU 32K FLASH MEM 32-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F34xr

Specifications of C8051F347-GM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F340DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1348-5

Bits7:
Bit6:
Bits5–0: USBADDR: USB0 Indirect Register Address
BUSY
R/W
Bit7
BUSY: USB0 Register Read Busy Flag
This bit is used during indirect USB0 register accesses. Software should write ‘1’ to this bit to
initiate a read of the USB0 register targeted by the USBADDR bits (USB0ADR.[5-0]). The
target address and BUSY bit may be written in the same write to USB0ADR. After BUSY is
set to ‘1’, hardware will clear BUSY when the targeted register data is ready in the
USB0DAT register. Software should check BUSY for ‘0’ before writing to USB0DAT.
Write:
0: No effect.
1: A USB0 indirect register read is initiated at the address specified by the USBADDR bits.
Read:
0: USB0DAT register data is valid.
1: USB0 is busy accessing an indirect register; USB0DAT register data is invalid.
AUTORD: USB0 Register Auto-read Flag
This bit is used for block FIFO reads.
0: BUSY must be written manually for each USB0 indirect register read.
1: The next indirect register read will automatically be initiated when software reads
USB0DAT (USBADDR bits will not be changed).
These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 16.2
lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT
will target the register indicated by the USBADDR bits.
AUTORD
R/W
Bit6
SFR Definition 16.2. USB0ADR: USB0 Indirect Address
R/W
Bit5
C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
R/W
Bit4
Rev. 1.3
R/W
Bit3
USBADDR
R/W
Bit2
R/W
Bit1
R/W
Bit0
SFR Address:
00000000
Reset Value
0x96
163