M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 128

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
12.5 Channel Priority and DMA Transfer Timing
Figure 12.6 DMA Transfer by External Sources
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to 1 (DMA requested) at the same time. In this case, the DMA
requests are arbitrated according to the channel priority, DMA0 > DMA1.
The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the same
sampling period.
Figure 12.6 shows an example of DMA Transfer by External Sources.
In Figure 12.6, DMA0 request having priority is received first to start a transfer when a DMA0 request and
DMA1 request are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is
returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one
DMA1 transfer is completed, the bus arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 12.6, occurs more than one time, the DMAS bit is set to 0 as soon as
getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
Refer to 7.2.7 HOLD Signal for details about bus arbitration between the CPU and DMA.
An example where DMA requests for external sources are detected active at the same time,
a DMA transfer is executed in the shortest cycle.
INT0
INT1
BCLK
DMA0
DMA1
CPU
DMA0
request bit
DMA1
request bit
Apr 14, 2006
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Bus arbitration
12. DMAC