M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 214

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 15.19 SI/O3 Specifications
NOTES:
Transfer data format
Transfer clock
Transmit/receive
start condition
Interrupt request
generation timing
CLK3 pin function
SOUT3 pin function
SIN3 pin function
Select function
1. To set the SM36 bit in the S3C register to 0 (external clock), follow the procedure described below.
2. Unlike UART0 to UART2, SI/O3 is not separated between the transfer register and buffer. Therefore,
3. When the SM36 bit = 1 (internal clock), SOUT3 retains the last data for a 1/2 transfer clock period after
4. When the SM36 bit = 1 (internal clock), the transfer clock stops in the high state if the SM34 bit = 0, or
• If the SM34 bit in the S3C register = 0, write transmit data to the S3TRR register while input on the
• If the SM34 bit = 1, write transmit data to the S3TRR register while input on the CLK3 pin is low. The
• Because shift operation continues as long as the transfer clock is supplied to the SI/O3 circuit, stop
do not write the next transmit data to the S3TRR register during transmission.
completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the S3TRR register during this period, SOUT3 immediately goes to a high-impedance state,
with the data hold time thereby reduced.
stops in the low state if the SM34 bit = 1.
CLK3 pin is high. The same applies when rewriting the SM37 bit in the S3C register.
same applies when rewriting the SM37 bit.
the transfer clock after supplying eight pulses. If the SM36 bit = 1 (internal clock), the transfer clock
automatically stops.
Apr 14, 2006
Item
page 190 of 376
Transfer data length: 8 bits
• SM36 bit in S3C register = 1 (internal clock) : fj/(2(n+1))
• SM36 bit = 0 (external clock) : Input from CLK3 pin
Before transmission/reception can start, meet the following requirements
• When SM34 bit in S3C register = 0
• When SM34 bit = 1
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
• LSB first or MSB first selection
• Function for setting an SOUT3 initial value set function
• CLK polarity selection
fj = f1SIO, f8SIO, f32SIO. n = Setting value of S3BRG register 00h to FFh
Write transmit data to the S3TRR register
The rising edge of the last transfer clock pulse
The falling edge of the last transfer clock pulse
Whether to start transmitting or receiving data begins with bit 0 or begins
with bit 7 can be selected
When the SM36 bit in the S3C register = 0 (external clock), the SOUT3 pin
output level while not transmitting can be selected.
Whether transmit data is output/input timing at the rising edge or falling
edge of transfer clock can be selected.
Specification
(2) (3)
(4)
(4)
(1)
15. Serial Interface