M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 257

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
19.12 Return from Bus Off Function
19.13 Time Stamp Counter and Time Stamp Function
19.14 Listen-Only Mode
When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by
setting the RetBusOff bit in the CiCTLR register (i = 0, 1) to 1 (force return from bus off). At this time, the
error state changes from bus off state to error active state. If the RetBusOff bit is set to 1, registers CiRECR
and CiTECR are initialized and the State_BusOff bit in the CiSTR register is set to 0 (CAN module is not in
error bus off state). However, registers of the CAN module such as CiCONR register and the content of
each slot are not initialized.
When the CiTSR register ( i = 0, 1) is read, the value of the time stamp counter at the moment is read. The
period of the time stamp counter reference clock is the same as that of 1 bit time that is configured by the
CiCONR register. The time stamp counter functions as a free run counter.
The 1 bit time period can be divided by 1 (undivided), 2, 4 or 8 to produce the time stamp counter reference
clock. Use the TSPreScale bit in the CiCTLR register to select the divide-by-n value.
The time stamp counter is equipped with a register that captures the counter value when the protocol
controller regards it as a successful reception. The captured value is stored when a time stamp value is
stored in a reception slot.
When the RXOnly bit in the CiCTLR register ( i = 0, 1) is set to 1, the module enters Listen-only mode.
In Listen-only mode, no transmission, such as data frames, error frames, and ACK response, is performed
to bus.
When Listen-only mode is selected, do not request the transmission.
Apr 14, 2006
page 233 of 376
19. CAN Module