HD6417041AVF16V Renesas Electronics America, HD6417041AVF16V Datasheet - Page 55
HD6417041AVF16V
Manufacturer Part Number
HD6417041AVF16V
Description
IC SUPERH MCU ROMLESS 144QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7040r
Specifications of HD6417041AVF16V
Core Processor
SH-2
Core Size
32-Bit
Speed
28.7MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417041AVF16V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.5.3
Like other DSPs, the SH-DSP has a modulo addressing mode. Address registers are updated in the
same way in this mode. When a modulo end address in which the address pointer value is already
set is reached, the address pointer becomes the modulo start address.
Modulo addressing is only effective for X and Y data transfer instructions (MOVX.W and
MOVY.W). When the DMX bit of the SR register is set, the X address register enters modulo
addressing mode; when the DMY bit is set, the Y address register enters modulo addressing mode.
Modulo addressing cannot be used on both X and Y address registers at once. Accordingly, do not
set DMX and DMY at the same time. Should they both be set at once, only DMY will be valid.
The MOD register is provided for specifying the start and end addresses for the modulo address
area. The MOD register stores the MS (modulo start) and ME (modulo end). The following shows
how to use the modulo register (MS and ME).
Note: There are four addressing methods (no update, index register addition (Is),
Modulo Addressing
increment, and decrement). Index register addition and increment are
post-increment methods. Decrement is a pre-decrement method.
+2/+4 (INC)
+0 (No update)
–2/–4 (DEC)
Figure 4.2 Single Data Transfer Addressing
R8[Is]
ALU
R2[As]
R3[As]
R4[As]
R5[As]
Rev. 5.00 Jun 30, 2004 page 39 of 512
Section 4 Instruction Features
REJ09B0171-0500O
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