MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 893

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.5.4.2
Doublewords 1 and 2 specify static information about the full-speed endpoint, the addressing of the parent
companion controller, and micro-frame scheduling control.
32.5.4.3
Doublewords 3-6 are used to manage the state of the transfer.
Freescale Semiconductor
Hub Address
Port Number
Address
C-mask
µFrame
µFrame
S-mask
Device
EndPt
30:24
22:16
15:12
31:16
11:8
15:8
Bit
I/O
6:0
Bit
7:0
31
23
7
siTD Endpoint Capabilities/Characteristics
siTD Transfer State
Direction (I/O). This field encodes whether the full-speed transaction should be an IN or OUT.
0 OUT
1 IN
This field is the port number of the recipient transaction translator.
Reserved. Bit reserved and should be cleared.
This field holds the device address of the companion controller’s hub.
Reserved. Field reserved and should be cleared.
Endpoint Number. This 4-bit field selects the particular endpoint number on the device serving as the data
source or sink.
Reserved. Bit is reserved for future use. It should be cleared.
This field selects the specific device serving as the data source or sink.
Reserved. This field reserved for future use. It should be cleared.
Split Completion Mask. This field (along with the active and SplitX- state fields in the status byte) is used to
determine during which micro-frames the host controller should execute complete-split transactions. When the
criteria for using this field is met, an all zeros value has undefined behavior. The host controller uses the value
of the three low-order bits of the USB_FRINDEX register to index into this bit field. If the USB_FRINDEX
register value indexes to a position where the µFrame C-Mask field is a one, then this siTD is a candidate for
transaction execution. There may be more than one bit in this mask set.
Split Start Mask. This field (along with the active and SplitX-state fields in the status byte) is used to determine
during which micro-frames the host controller should execute start-split transactions. The host controller uses
the value of the three low-order bits of the USB_FRINDEX register to index into this bit field. If the
USB_FRINDEX register value indexes to a position where the µFrame S-mask field is a one, then this siTD is
a candidate for transaction execution. An all zeros value in this field, in combination with existing periodic frame
list has undefined results.
Table 32-51. Endpoint and Transaction Translator Characteristics
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-52. Micro-frame Schedule Control
Description
Description
Universal Serial Bus Interface with On-The-Go
32-65