MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 955

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Managing the QH[FrameTag] Field
The QH[FrameTag] field in a queue head is completely managed by the host controller. The rules for
setting QH[FrameTag] are simple:
32.6.11.2.5 Rebalancing the Periodic Schedule
System software must occasionally adjust a periodic queue head's S-mask and C-mask fields during
operation. This need occurs when adjustments to the periodic schedule create a new bandwidth budget and
one or more queue head's are assigned new execution footprints (new S-mask and C-mask values).
It is imperative that system software not update these masks to new values in the midst of a split
transaction. To avoid any race conditions with the update, the host controller provides a simple assist to
system software. System software sets the inactivate-on-next-transaction (I) bit to signal the host controller
it intends to update the S-mask and C-mask on this queue head. System software then waits for the host
controller to observe the I-bit is set and transitions the active bit to a zero. The rules for how and when the
host controller clears the active bit are:
Freescale Semiconductor
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Rule 1: If transitioning from Do Start Split to Do Complete Split and the current value of
USB_FRINDEX[2:0] is 6, QH[FrameTag] is set to USB_FRINDEX[7:3] + 1. This accommodates
split transactions whose start-split and complete-splits are in different H-Frames (case 2a, see
Figure
Rule 2: If the current value of USB_FRINDEX[2:0] is 7, QH[FrameTag] is set to
USB_FRINDEX[7:3] + 1. This accommodates staying in Do Complete Split for cases 2a, 2b, and
2c in
Rule 3: If transitioning from Do_Start Split to Do Complete Split and the current value of
USB_FRINDEX[2:0] is not 6, or currently in Do Complete Split and the current value of
(USB_FRINDEX[2:0]) is not 7, FrameTag is set to USB_FRINDEX[7:3]. This accommodates all
other cases in
If the active bit is cleared, no action is taken. The host controller does not attempt to advance the
queue when the I-bit is set.
If the active bit is set and the SplitXState is DoStart (regardless of the value of S-mask), the host
controller simply clears the active bit. The host controller is not required to write the transfer state
If PIDCode = IN
Halt QHDIf PIDCode = OUT
Retry start-split
Table 32-76. Interrupt IN/OUT Do Complete Split State Execution Criteria (continued)
Figure
32-64).
Action
32-64.
Figure
32-64.
MPC5125 Microcontroller Reference Manual, Rev. 2
This is a degenerate case where the start-split was issued, but all of the
complete-splits were skipped and all possible intervening opportunities to detect the
missed data failed to fire. If PID Code is an IN, the queue head must be halted. If PID
code is an OUT, then the transfer state is not advanced and the state exited (for
example, start-split is retried). This is a host-induced error and does not affect Cerr.
In either case, set the missed micro-frame bit in the status field to a one. When
executing in the context of a recovery path mode, the host controller can process the
queue head and take the actions indicated above or it may wait until the queue head
is visited in the normal processing mode. Regardless, the host controller must not
execute a start-split in the context of an executing in a recovery path mode.
Description
Universal Serial Bus Interface with On-The-Go
32-127