MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 99

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6.5
The Reset Protection Register (RPR), shown in
Register (RCR). This register prevents unwanted resets due to unintended software writes to the Reset
Control Register (RCR). The user should write the value 0x5253_5445 (RSTE in ASCII) to enable. Enable
indication appears in the Reset Control Enable Register (RCER[CRE]). Reading this register always
returns all 0s. To disable writing to the Reset Control Register (RCR), write a 1 to RCER[CRE].
4.6.6
The Reset Control Register (RCR) shown in
reset sequence. To allow writing to this register, the user must first write the value 0x5253_5445 to the
Reset Protection Register (RPR).
Freescale Semiconductor
Address: Base + 0x18
Reset
Reset
RCPW
CSRE
Field
Field
W
W
R
R
16
0
0
0
Reset Protection Register (RPR)
Reset Control Register (RCR)
Checkstop reset enable. The e300 core can enter checkstop mode as the result of several exception
conditions. Setting CSRE configures the chip to perform a hard reset sequence whenever the e300 core
enters checkstop state.
0 Reset is not generated when the core enters checkstop state.
1 Reset is generated when the core enters checkstop state.
Reset control protection word. This register prevents software reset requests from occurring because of
unintended writes to the Reset Control Register (RCR). To enable write protection, write 0x5253_5445 (RSTE
in ASCII) to this bitfield. Enable indication appears in the Reset Control Enable Register (RCER[CRE]).
Reading this register always returns all 0s. To disable write to the RCR, write 1 to RCER[CRE].
17
0
0
1
18
0
0
2
19
0
0
3
Table 4-11. RMR field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 4-6. Reset Protection Register (RPR)
20
4
0
0
Table 4-12. RPR field descriptions
21
0
0
5
Figure 4-7
Figure
22
0
0
6
23
0
0
7
4-6, enables or disables writing to the Reset Control
RCPW
RCPW
Description
Description
can be used by software to initiate a soft or hard
24
8
0
0
25
9
0
0
10
26
0
0
11
27
0
0
12
28
0
0
Access: User read/write
13
29
0
0
14
30
0
0
Reset
15
31
4-13
0
0