MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 899

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Status
7:0
Bit
The host controller uses this field to communicate individual command execution states back to the host
controller driver (HCD) software. This field contains the status of the last transaction performed on this qTD.
The bit encodings are:
Bit
7
6
5
4
3
2
1
0
Table 32-59. qTD Token (doubleword 2) (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Active. Set by software to enable the execution of transactions by the host controller.
Halted. Set by the host controller during status updates to indicate that a serious error has
occurred at the device/endpoint addressed by this qTD. This can be caused by babble, the
error counter counting down to zero, or reception of the STALL handshake from the device
during a transaction. Any time a transaction results in the halted bit being set, the active bit
is also cleared.
Data Buffer Error. Set by the host controller during status update to indicate the host
controller is unable to keep up with the reception of incoming data (overrun) or is unable to
supply data fast enough during transmission (under run). If an overrun condition occurs, the
host controller forces a time-out condition on the USB, invalidating the transaction at the
source. If the host controller sets this bit to a one, it remains a one for the duration of the
transfer.
Babble Detected. Set by the host controller during status update when babble is detected
during the transaction. In addition to setting this bit, the host controller also sets the halted
bit to a one. Because babble is considered a fatal error for the transfer, setting the halted
bit to a one ensures no more transactions occur because of this descriptor.
Transaction Error (XactErr). Set by the host controller during status update in the case
where the host did not receive a valid response from the device (time-out, CRC, bad PID).
If the host controller sets this bit to a one, it remains a one for the duration of the transfer.
Missed Micro-Frame. This bit is ignored unless the QH[EPS] field indicates a full- or
low-speed endpoint and the queue head is in the periodic list. This bit is set when the host
controller detects a host-induced hold-off caused the host controller to miss a required
complete-split transaction. If the host controller sets this bit to a one, it remains a one for
the duration of the transfer.
Split Transaction State (SplitXstate). This bit is ignored by the host controller unless the
QH[EPS] field indicates a full- or low-speed endpoint. When configured as a full- or
low-speed device, the host controller uses this bit to track the state of the split- transaction.
The functional requirements of the host controller for managing this state bit and the split
transaction protocol depends on whether the endpoint is in the periodic or asynchronous
schedule. The bit encodings are:
0 Do Start Split. This value directs the host controller to issue a start split transaction to the
1 Do Complete Split. This value directs the host controller to issue a complete split
Ping State (P)/ERR. If the QH[EPS] field indicates a high-speed device and the PID Code
indicates an OUT endpoint, this is the state bit for the ping protocol. The bit encodings are:
0 Do OUT. This value directs the host controller to issue an OUT PID to the endpoint.
1 Do Ping. This value directs the host controller to issue a PING PID to the endpoint.
If the QH[EPS] field does not indicate a high-speed device, this field is used as an error
indicator bit. It is set by the host controller when a periodic split-transaction receives an ERR
handshake.
endpoint.
transaction to the endpoint.
Description
Status Field Description
Universal Serial Bus Interface with On-The-Go
32-71