HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 228

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2.4
Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
TCSR is initialized to H'10 by a reset and in the standby modes.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 7: CMFB
0
1
Bit 6—Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 6: CMFA
0
1
Bit 5—Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows
(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 5: OVF
0
1
196
Bit
Initial value
Read/Write
Timer Control/Status Register (TCSR)
R/(W)*
CMFB
Description
To clear CMFB, the CPU must read CMFB after it has been set to 1 then write
a 0 in this bit.
This bit is set to 1 when TCNT = TCORB.
Description
To clear CMFA, the CPU must read CMFA after it has been set to 1, then write
a 0 in this bit.
This bit is set to 1 when TCNT = TCORA.
Description
To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0
in this bit.
This bit is set to 1 when TCNT changes from H'FF to H'00.
7
0
R/(W)*
CMFA
6
0
R/(W)*
OVF
5
0
—
—
4
1
OS3
R/W
3
0
R/W
OS2
2
0
OS1
R/W
1
0
(Initial value)
(Initial value)
(Initial value)
OS0
R/W
0
0