HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 275

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 0—Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode,
this bit enables or disables serial clock output at the SCK pin.
This bit is ignored when the external clock is selected, or when synchronous mode is selected.
For further information on the communication format and clock source selection, see table 12.8 in
section 12.3, Operation.
Bit 0: CKE0
0
1
12.2.7
Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits.
SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 by a reset
and in the standby modes.
Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when transmit data can safely
be written in TDR.
Bit 7: TDRE
0
1
Bit
Initial value
Read/Write
Serial Status Register (SSR)
R/(W)*
TDRE
Description
The SCK pin is not used by the SCI (and is available as a general-purpose I/O
port).
The SCK pin is used for serial clock output.
Description
To clear TDRE, the CPU must read TDRE after it has been set to 1, then write
a 0 in this bit.
This bit is set to 1 at the following times:
1. When TDR contents are transferred to TSR.
2. When the TE bit in SCR is cleared to 0.
7
1
R/(W)*
RDRF
6
0
R/(W)*
ORER
5
0
R/(W)*
FER
4
0
R/(W)*
PER
3
0
TEND
2
1
R
MPB
1
0
R
(Initial value)
(Initial value)
MPBT
R/W
0
0
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