HD64F3437TFI16V Renesas Electronics America, HD64F3437TFI16V Datasheet - Page 476

• Manufacturer Part Number: HD64F3437TFI16V
• Description: MCU FLASH 60K 100-TQFP
• Manufacturer: Renesas Electronics America

Specifications of HD64F3437TFI16V

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.2.4
WSCR is an 8-bit readable/writable register that enables flash-memory updates to be emulated in
RAM. It also controls frequency division of clock signals supplied to the on-chip supporting
modules and insertion of wait states by the wait-state controller.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—RAM Select and RAM0 (RAMS and RAM0): These bits are used to reassign an
area to RAM (see table 20.5). These bits are write-enabled and their initial value is 0. They are
initialized by a reset and in hardware standby mode. They are not initialized in software standby
mode.
If only one of bits 7 and 6 is set, part of the RAM area can be overlapped onto the small-block
flash memory area. In that case, access is to RAM, not flash memory, and all flash memory blocks
are write/erase-protected (emulation protect
program or erase mode, even if the P bit or E bit in the flash memory control register (FLMCR) is
set (although verify mode can be selected). Therefore, clear both of bits 7 and 6 before
programming or erasing the flash memory area.
If both of bits 7 and 6 are set, part of the RAM area can be overlapped onto the small-block flash
memory area, but this overlapping begins only when an interrupt signal is input while 12 V is
being applied to the FV
interrupt handling while flash memory is being programmed or erased.
Table 20.5 RAM Area Reassignment
Bit 7: RAMS
0
1
444
Bit
Initial value
Read/Write
Wait-State Control Register (WSCR)
RAMS
R/W
Bit 6: RAM0
0
1
0
1
7
0
PP
pin. Up until that point, flash memory is accessed. Use this setting for
RAM0
R/W
6
0
CKDBL
R/W
RAM Area
None
H'F880 to H'F8FF
H'F880 to H'F97F
H'F800 to H'F87F
*3
5
0
*1
). In this state, the mode cannot be changed to
R/W
—
4
0
WMS1
R/W
3
1
WMS0
ROM Area
—
H'0080 to H'00FF
H'0080 to H'017F
H'0000 to H'007F
*2
R/W
2
0
WC1
R/W
1
0
WC0
R/W
0
0