M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 79

• Manufacturer Part Number: M30833FJGP#U5
• Description: IC M32C/83 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJGP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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M
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3
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Table 7.2 Processor Mode and Port Function
2
Data Bus Width
NOTES:
0
PM0 Register
C
1
P0
P1
P2
P3
P4
P4
P4
P5
P5
P5
P5
P5
PM04 Bits in
9
Processor
3 .
B
8 /
PM05 to
1. The PM05 to PM04 bits cannot be set to "11
2. These ports become address buses when accessing space using the separate bus.
3. The PM15 to PM14 bits in the PM1 register determine which pin outputs the ALE signal. The PM02 bit in
4. When DRAMC is selected to access DRAM area, CASL, CASH, DW, BCLK become output pins.
5. The PM11 to PM10 bits in the PM1 register determine the CS signal and address bus.
Mode
0
0
0
0
0
4
7
0
4
5
6
7
0
1
3
to P0
to P1
to P2
to P3
to P4
to P4
to P5
0
microprocessor mode because the microcomputer starts operation using the separate bus after reset.
When the PM05 to PM04 bits are set to "11
64K-byte memory space per chip select using the address bus .
the PM0 register selects either "WRL,WRH" or "BHE,WR" combination. P5
output when the PM15 and PM14 bits to "00
3
J
G
4
a
o r
0 -
n
7
7
7
7
3
6
3
3 .
1
u
, 1
3
p
1
Chip Mode
(
2
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
M
Single-
0
0
3
6
2
C
8 /
Page 54
, 3
external space with
Address bus/
Data bus
A
Access All Other CS Areas using
CS (Chip-select signal) or Address bus (A
CS (Chip-select signal) or Address bus (A
Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK
M
8-bit data bus
0
Address bus
Address bus
/D
Data bus
Access all
A
HOLD
A
HLDA
3
D
Access CS1 or CS2 using
I/O port
16
RDY
RAS
0
8
2
0
to
to
the Multiplexed Bus
to
C
to
f o
the Separate Bus
A
(Refer to 7.2 Bus Control for details)
A
(2)
D
8 /
A
Memory Expansion Mode/ Microprocessor Mode
"01
7
15
(3)
7
19
(3)
/D
4
3
8
7
) T
2
8
", "10
Access one or more
external space with
Address bus/
Data bus
A
(Refer to 7.2 Bus Control for details)
Address bus/
Data bus
A
16-bit data bus
8
Address bus
2
0
/D
Data bus
A
"
Data bus
/D
D
D
HOLD
HLDA
8
16
2
8
RAS
RDY
0
2
0
2
" in memory expansion mode, the microcomputer accesses
to
" (access all CS areas using multiplexed bus) in
" (no ALE). It cannot be used as an I/O port.
to
to
to
to
A
(2)
D
A
(Refer to 7.2 Bus Control for details)
D
A
(2)
15
7
15
19
7
(3)
(3)
/D
/D
7
15
external space with
Address bus
Address bus
Address bus
8-bit data bus
A
Data bus
A
Access all
A
I/O port
HOLD
D
Access all CS Areas using
16
8
HLDA
0
RDY
RAS
0
to
to
to
to
A
the Separate Bus
A
A
D
15
23
20
7
19
7
(3)
(3)
(3)
)
to A
"00
Access one or more
22
2
external space with
"
Address bus
16-bit data bus
)
Address bus
Address bus
Data bus
6
A
Data bus
D
(4)
D
A
16
A
HLDA
HOLD
provides an indeterminate
8
RAS
RDY
8
0
0
to
to
to
to
to
D
A
A
D
A
15
19
15
7
(3)
7
(3)
(4)
external space with
Address bus/
Data bus
A
Address bus
0
8-bit data bus
/D
Memory Expansion Mode
A
Access all
I/O port
I/O port
I/O port
HOLD
Access all CS Areas using
HLDA
8
RAS
0
RDY
to
to
the Multiplexed Bus
A
A
15
7
(3)
/D
(3)
7
"11
Access one or more
Address bus/
Data bus
A
external space with
2
Address bus/
Data bus
A
"
8
16-bit data bus
(1)
/D
0
/D
8
I/O port
I/O port
I/O port
HOLD
HLDA
0
RDY
to
RAS
to
A
A
15
7
/D
/D
(3)
(3)
15
7
7. Bus