ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 78
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ATTINY40-MMHR
Manufacturer Part Number
ATTINY40-MMHR
Description
MCU AVR 4KB FLASH 12MHZ 3X3 QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY40-MMHR.pdf
(216 pages)
Specifications of ATTINY40-MMHR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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ATtiny40
Table 11-6
Table 11-6.
Note:
Table 11-7
correct PWM mode.
Table 11-7.
Note:
• Bits 3:2 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
COM0B1
COM0B1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
shows COM0B[1:0] bit functionality when WGM0[2:0] bits are set to fast PWM mode.
pare Match is ignored, but the set or clear is done at BOTTOM. See
page 71
pare Match is ignored, but the set or clear is done at TOP. See
page 73
shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase
Compare Output Mode, Fast PWM Mode
Compare Output Mode, Phase Correct PWM Mode
COM0B0
COM0B0
for more details.
for more details.
0
1
0
1
0
1
0
1
Description
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match, set OC0B at BOTTOM
(non-inverting mode)
Set OC0B on Compare Match, clear OC0B at BOTTOM
(inverting mode)
Description
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Table
11-8. Modes of operation supported by the Timer/Counter
“Modes of Operation” on page
(1)
(1)
“Phase Correct PWM Mode” on
“Fast PWM Mode” on
70).
8263A–AVR–08/10
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