ATTINY40-MMHR Atmel, ATTINY40-MMHR Datasheet - Page 97

• Manufacturer Part Number: ATTINY40-MMHR
• Description: MCU AVR 4KB FLASH 12MHZ 3X3 QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY40-MMHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.10.7
8263A–AVR–08/10
TIFR – Timer/Counter1 Interrupt Flag Register
• Bit 7 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set to be used as the TOP value, the ICF1 flag is set when the counter reaches the
TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 6 – Res: Reserved Bit
This bit is reserved and will always read as zero.
• Bit 5 – OCF1B: Output Compare Flag 1 B
The OCF1B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR1B – Output Compare Register1 B. OCF1B is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE1B (Timer/Counter Compare B Match Interrupt Enable),
and OCF1B are set, the Timer/Counter Compare Match Interrupt is executed.
The OCF1B is not set in 16-bit Output Compare mode when the Output Compare Register
OCR1B is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-
ture mode when the Output Compare Register OCR1B is used as the high byte of the Input
Capture Register.
• Bit 4 – OCF1A: Output Compare Flag 1 A
The OCF1A bit is set when a Compare Match occurs between the Timer/Counter1 and the data
in OCR1A – Output Compare Register1. OCF1A is cleared by hardware when executing the cor-
responding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE1A (Timer/Counter1 Compare Match Interrupt Enable),
and OCF1A are set, the Timer/Counter1 Compare Match Interrupt is executed.
The OCF1A is also set in 16-bit mode when a Compare Match occurs between the Timer/Coun-
ter and 16-bit data in OCR1B/A. The OCF1A is not set in Input Capture mode when the Output
Compare Register OCR1A is used as an Input Capture Register.
• Bit 3 – TOV1: Timer/Counter1 Overflow Flag
The bit TOV1 is set when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE1 (Timer/Counter1 Overflow Interrupt
Enable), and TOV1 are set, the Timer/Counter1 Overflow interrupt is executed.
Bit
0x25
Read/Write
Initial Value
ICF1
R/W
7
0
R
6
–
0
OCF1B
R/W
5
0
OCF1A
R/W
4
0
TOV1
R/W
3
0
OCF0B
R/W
2
0
OCF0A
R/W
1
0
TOV0
R/W
0
0
TIFR
97