ATMEGA64M1-AU Atmel, ATMEGA64M1-AU Datasheet - Page 148
![IC MCU AVR 64K FLASH 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA64M1-AU
Manufacturer Part Number
ATMEGA64M1-AU
Description
IC MCU AVR 64K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA64M1-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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17.16.3
17.16.4
17.16.5
148
ATmega16M1/32M1/64M1
POCRnSAH and POCRnSAL – PSC Output Compare SA Register
POCRnRAH and POCRnRAL – PSC Output Compare RA Register
POCRnSBH and POCRnSBL – PSCOutput Compare SB Register
• Bit 1:0 – PSYNC0[1:0]: Synchronization Out for ADC Selection
Select the polarity and signal source for generating a signal which will be sent from module 0 to
the ADC for synchronization.
Table 17-8.
Table 17-9.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
PSYNCn1
0
0
1
1
PSYNCn1
0
0
1
1
Synchronization Source Description in One Ramp Mode
Synchronization Source Description in Centered Mode
PSYNCn0
0
1
0
1
PSYNCn0
0
1
0
1
R/W
R/W
R/W
7
–
0
7
–
0
7
–
0
R/W
R/W
R/W
6
–
0
6
–
0
6
–
0
Description
Send signal on match with OCRnRA (during counting down of PSC). The
min value of OCRnRA must be 1
Send signal on match with OCRnRA (during counting up of PSC). The
min value of OCRnRA must be 1
no synchronization signal
no synchronization signal
Description
Send signal on leading edge of PSCOUTnA(match with OCRnSA)
Send signal on trailing edge of PSCOUTnA(match with OCRnRA or
fault/retrigger on part A)
Send signal on leading edge of PSCOUTnB (match with OCRnSB)
Send signal on trailing edge of PSCOUTnB (match with OCRnRB or
fault/retrigger on part B)
R/W
R/W
R/W
5
–
0
5
–
0
5
–
0
R/W
R/W
R/W
POCRnSA[7:0]
POCRnRA[7:0]
POCRnSB[7:0]
4
–
0
4
–
0
4
–
0
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
POCRnSA[11:8]
POCRnRA[11:8]
POCRnSB[11:8]
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
0
0
0
0
0
0
8209D–AVR–11/10
POCRnSAH
POCRnRAH
POCRnRAL
POCRnSBH
POCRnSAL
POCRnSBL
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