ATMEGA64M1-AU Atmel, ATMEGA64M1-AU Datasheet - Page 195

IC MCU AVR 64K FLASH 32TQFP

ATMEGA64M1-AU

Manufacturer Part Number
ATMEGA64M1-AU
Description
IC MCU AVR 64K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64M1-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64M1-AU
Manufacturer:
Atmel
Quantity:
10 000
19.11.5
19.11.6
19.12 Examples of CAN Baud Rate Setting
8209D–AVR–11/10
CANSTML and CANSTMH – CAN Time Stamp Registers
CANMSG – CAN Data Message Register
• Bit 2 – RTRMSK: Remote Transmission Request Mask
• Bit 1 – Reserved Bit
Writing zero in this bit is recommended.
• Bit 0 – IDEMSK: Identifier Extension Mask
• Bits 15:0 - TIMSTM[15:0]: Time Stamp Count
CAN time stamp counter range 0 to 65,535.
• Bit 7:0 – MSG[7:0]: Message Data
This register contains the CAN data byte pointed at the page MOb register.
After writing in the page MOb register, this byte is equal to the specified message location of the
pre-defined identifier + index. If auto-incrementation is used, at the end of the data register writ-
ing or reading cycle, the index is auto-incremented.
The range of the counting is 8 with no end of loop (0, 1,..., 7, 0,...).
The CAN bus requires very accurate timing especially for high baud rates. It is recommended to
use only an external crystal for CAN operations.
(Refer to
186
Initial Value
Read/Write
Initial Value
Read/Write
to
Bit
Bit
– 0 - comparison true forced
– 1 - bit comparison enabled
– 0 - comparison true forced
– 1 - bit comparison enabled
Bit
page 188
“Bit Timing” on page 170
TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10
TIMSTM7
MSG 7
15
R/W
R
7
-
for “CAN Bit Timing Registers”).
7
-
TIMSTM6
MSG 6
14
R/W
6
R
-
6
-
TIMSTM5
MSG 5
R/W
13
R
and
5
-
5
-
“Baud Rate” on page 172
TIMSTM4
MSG 4
R/W
12
R
4
-
4
-
ATmega16M1/32M1/64M1
TIMSTM3
MSG 3
R/W
11
R
3
-
3
-
TIMSTM2
MSG 2
R/W
10
R
2
-
2
-
for timing description and
TIMSTM1
TIMSTM9
MSG 1
R/W
R
1
9
-
1
-
TIMSTM8
TIMSTM0
MSG 0
R/W
R
0
8
-
0
-
CANSTMH
CANSTML
CANMSG
page
195

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