ATMEGA64M1-AU Atmel, ATMEGA64M1-AU Datasheet - Page 32

IC MCU AVR 64K FLASH 32TQFP

ATMEGA64M1-AU

Manufacturer Part Number
ATMEGA64M1-AU
Description
IC MCU AVR 64K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA64M1-AU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA64M1-AU
Manufacturer:
Atmel
Quantity:
10 000
8.7
32
128kHz Internal Oscillator
ATmega16M1/32M1/64M1
Therefore it is recommended not to take the OSCCAL adjustments to a higher frequency than 1
MHz in order to keep the PLL in the correct operating range. The internal PLL is enabled only
when the PLLE bit in the register PLLCSR is set. The bit PLOCK from the register PLLCSR is
set when PLL is locked.
Both internal 1MHz RC Oscillator and PLL are switched off in Power-down and Standby sleep
modes.
Table 8-7.
Note:
Figure 8-3.
The 128kHz internal Oscillator is a low power Oscillator providing a clock of 128kHz. The fre-
quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator.
RC Osc
Ext Osc
CKSEL
Ext Clk
0011
0101
0001
3..0
XTAL1
XTAL2
1. This value do not provide a proper restart ; do not use PD in this clock scheme
RC OSCILLATOR
SUT1..0
OSCCAL
Start-up Times when the PLL is selected as system clock
PCK Clocking System
00
01
10
11
00
01
10
11
00
01
10
11
OSCILLATORS
8 MHz
Start-up Time from Power-down
and Power-save
DIVIDE
BY 8
16K CK
16K CK
16K CK
6 CK
6 CK
6 CK
1K CK
1K CK
1K CK
1K CK
1K CK
(1)
(1)
(1)
PLLE
PLL
64x
Detector
Lock
Reserved
DIVIDE
DIVIDE
PLLF
BY 2
BY 4
Additional Delay from Reset
14CK + 64ms
14CK + 64ms
14CK + 64ms
(V
14CK + 4ms
14CK + 4ms
14CK + 4ms
14CK + 4ms
CLK
CC
PLOCK
CK
14CK
14CK
14CK
14CK
PLL
= 5.0V)
SOURCE
8209D–AVR–11/10

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