DSPIC30F2020-30I/MMB32 Microchip Technology, DSPIC30F2020-30I/MMB32 Datasheet - Page 18
![IC DSPIC MCU/DSP 12K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2020-30I/MMB32
Manufacturer Part Number
DSPIC30F2020-30I/MMB32
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F1010-30ISO.pdf
(26 pages)
4.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020-30I/MMB32
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
Q4035438A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2020-30I/MMB32
Manufacturer:
Microchip Technology
Quantity:
135
- AC164335 PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F1010-30ISO PDF datasheet #3
- DSPIC30F1010-30ISO PDF datasheet #4
- Current page: 18 of 286
- Download datasheet (5Mb)
dsPIC30F1010/202X
FIGURE 1-3:
DS70178C-page 16
OSC1/CLK1
Control Signals
to Various Blocks
Program Memory
Controller
Address Latch
Interrupt
Data Latch
(12 Kbytes)
Comparator
Module
SPI1
24
Generation
Timing
Instruction
Decode &
Control
16
MCLR
24
24
Control Block
PSV & Table
Data Access
24
10-bit ADC
Timers
dsPIC30F2023 BLOCK DIAGRAM
16
Control
Start-up Timer
Stack
Logic
PCU
Program Counter
Watchdog
Power-up
Oscillator
Y Data Bus
Reset
Timer
Timer
POR
8
ROM Latch
Notification
PCH
Capture
Module
Change
IR
Input
Input
Control
Logic
Loop
16
PCL
Decode
16
Power Supply
Engine
16
DSP
Compare
Output
Module
PWM
Data Latch
(256 bytes)
Y AGU
Address
Y Data
Effective Address
Preliminary
Latch
RAM
16
16
16
W Reg Array
16
ALU<16>
16 x 16
16
16
16
X RAGU
X WAGU
X Data Bus
16
Data Latch
Divide
(256 bytes)
UART1
Address
Unit
X Data
I
Latch
2
RAM
C™
16
16
16
16
PORTA
PORTD
PORTE
PORTG
PORTB
PORTF
© 2006 Microchip Technology Inc.
PWM3H/RE5
PGC1/EMUC1/PWM4L/T1CK/
U1ARX/CN0/RE6
SFLT1/RA8
SFLT2/INT0/OCFLTA/RA9
SFLT3/RA10
SFLT4/RA11
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PGD1/EMUD1/PWM4H/T2CK/
U1ATX/CN1/RE7
SCL/RG2
SDA/RG3
U1RX/RF2
U1TX/RF3
PGD2/EMUD2/SCK1/INT2/RF6
PGC/EMUC/SDI1/RF7
PGD/EMUD/SD01/RF8
SYNCI/RF14
SYNCO/SSI/RF15
AN8/CMP4C/RB8
AN9/EXTREF/CMP4D/RB9
AN10/IFLT4/RB10
AN11/IFLT2/RB11
PGC2/EMUC2/OC1/IC1/INT1/
RD0
OC2/RD1
AN0/CMP1A/CN2/RB0
AN1/CMP1B/CN3/RB1
AN2/CMP1C/CMP2A/CN4/RB2
AN3/CMP1D/CMP2B/CN5/RB3
AN4/CMP2C/CMP3A/CN6/RB4
AN5/CMP2D/CMP3B/CN7/RB5
AN6/CMP3C/CMP4A/
OSC1/CLKI/RB6
AN7/CMP3D/CMP4B/
OSC2/CLKO/RB7
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