DSPIC30F2020-30I/MM Microchip Technology, DSPIC30F2020-30I/MM Datasheet

IC DSPIC MCU/DSP 12K 28QFN

DSPIC30F2020-30I/MM

Manufacturer Part Number
DSPIC30F2020-30I/MM
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr

Specifications of DSPIC30F2020-30I/MM

Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Core Frequency
15MHz
Core Supply Voltage
3.3V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
21
Flash Memory Size
12KB
Supply Voltage Range
3V To 3.6V
Package
28QFN-S EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
21
Interface Type
I2C/SPI/UART
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2020-30I/MM
Manufacturer:
Microchip Technology
Quantity:
265
Part Number:
DSPIC30F2020-30I/MMB32
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
DSPIC30F2020-30I/MMB32
Manufacturer:
Microchip Technology
Quantity:
456
dsPIC30F1010/202X
Data Sheet
28/44-Pin High-Performance
Switch Mode Power Supply
Digital Signal Controllers
Preliminary
© 2006 Microchip Technology Inc.
DS70178C

Related parts for DSPIC30F2020-30I/MM

DSPIC30F2020-30I/MM Summary of contents

Page 1

... Microchip Technology Inc. dsPIC30F1010/202X Data Sheet 28/44-Pin High-Performance Switch Mode Power Supply Digital Signal Controllers Preliminary DS70178C ...

Page 2

... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 3

... Single-cycle Multiply-Accumulate (MAC) operation • 40-stage Barrel Shifter • Dual data fetch © 2006 Microchip Technology Inc. dsPIC30F1010/202X Peripheral Features: • High-current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • ...

Page 4

... SOIC 6K dsPIC30F1010 28 QFN-S 6K dsPIC30F2020 28 SDIP 12K dsPIC30F2020 28 SOIC 12K dsPIC30F2020 28 QFN-S 12K dsPIC30F2023 44 QFN 12K dsPIC30F2023 44 TQFP 12K DS70178C-page 2 Special Microcontroller Features: • Enhanced Flash program memory: - 10,000 erase/write cycle (min.) for industrial temperature range, 100k (typical) • Self-reprogrammable under software control • ...

Page 5

... Pin Diagrams 28-Pin SDIP and SOIC AN0/CMP1A/CN2/RB0 AN1/CMP1B/CN3/RB1 AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CN6/RB4 AN5/CMP2D/CN7/RB5 OSC1/CLKI/RB6 OSC2/CLKO/RB7 PGD1/EMUD1/T2CK/U1ATX/CN1/RE7 PGC1/EMUC1/EXTREF/T1CK/U1ARX/CN0/RE6 PGD2/EMUD2/SCK1/SFLT3/INT2/RF6 28-Pin QFN-S AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CN6/RB4 AN5/CMP2D/CN7/RB5 OSC1/CLKI/RB6 OSC2/CLKO/RB7 © 2006 Microchip Technology Inc. dsPIC30F1010/202X 1 28 MCLR PWM1L/RE0 4 25 PWM1H/RE1 5 24 PWM2L/RE2 PWM2H/RE3 6 23 RE4 ...

Page 6

... PGD1/EMUD1/PWM4H/T2CK/U1ATX/CN1/RE7 PGC1/EMUC1/EXTREF/PWM4L/T1CK/U1ARX/CN0/RE6 PGD2/EMUD2/SCK1/SFLT3/OC2/INT2/RF6 28-Pin QFN-S AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CMP3A/CN6/RB4 AN5/CMP2D/CMP3B/CN7/RB5 AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 AN7/CMP3D/CMP4B/OSC2/CLKO/RB7 DS70178C-page MCLR PWM1L/RE0 4 25 PWM1H/RE1 5 24 PWM2L/RE2 PWM2H/RE3 6 23 PWM3L/RE4 PWM3H/RE5 PGC/EMUC/SDI1/SDA/U1RX/RF7 12 17 PGD/EMUD/SDO1/SCL/U1TX/RF8 SFLT2/INT0/OCFLTA/RA9 PGC2/EMUC2/OC1/SFLT1/IC1/INT1/RD0 PWM2L/RE2 2 20 PWM2H/RE3 3 19 PWM3L/RE4 dsPIC30F2020 4 PWM3H/RE5 PGC/EMUC/SDI1/SDA/U1RX/RF7 Preliminary © 2006 Microchip Technology Inc. ...

Page 7

... Pin Diagrams 44-PIN QFN PGC/EMUC/SDI1/RF7 SYNCO/SS1/RF15 SFLT3/RA10 SFLT4/RA11 SDA/RG3 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 © 2006 Microchip Technology Inc. dsPIC30F1010/202X AN7/CMP3D/CMP4B/OSC2/CLKO/RB7 2 32 AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 3 31 AN8/CMP4C/RB8 dsPIC30F2023 6 28 AN10/IFLT4/RB10 7 27 AN11/IFLT2/RB11 8 26 AN5/CMP2D/CMP3B/CN7/RB5 9 25 AN4/CMP2C/CMP3A/CN6/RB4 AN3/CMP1D/CMP2B/CN5/RB3 10 24 AN2/CMP1C/CMP2A/CN4/RB2 Preliminary DS70178C-page 5 ...

Page 8

... Pin Diagrams 44-Pin TQFP PGC/EMUC/SDI1/RF7 SYNCO/SS1/RF15 SFLT3/RA10 SFLT4/RA11 SDA/RG3 PWM3H/RE5 PWM3L/RE4 PWM2H/RE3 PWM2L/RE2 DS70178C-page dsPIC30F2023 Preliminary AN7/CMP3D/CMP4B/OSC2/CLKO/RB7 AN6/CMP3C/CMP4A/OSC1/CLKI/RB6 AN8/CMP4C/RB8 AN10/IFLT4/RB10 AN11/IFLT2/RB11 AN5/CMP2D/CMP3B/CN7/RB5 AN4/CMP2C/CMP3A/CN6/RB4 AN3/CMP1D/CMP2B/CN5/RB3 AN2/CMP1C/CMP2A/CN4/RB2 © 2006 Microchip Technology Inc. ...

Page 9

... Msps Analog-to-Digital Converter (ADC) Module........................................................................................................ 169 17.0 SMPS Comparator Module ...................................................................................................................................................... 191 18.0 System Integration ................................................................................................................................................................... 197 19.0 Instruction Set Summary .......................................................................................................................................................... 219 20.0 Development Support............................................................................................................................................................... 227 21.0 Electrical Characteristics .......................................................................................................................................................... 231 22.0 Package Marking Information................................................................................................................................................... 267 © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary DS70178C-page 7 ...

Page 10

... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70178C-page 8 Preliminary © 2006 Microchip Technology Inc. ...

Page 11

... Figure 1-1 and Table 1-1 describe the dsPIC30F1010 SMPS device, Figure 1-2 and Table 1-2 describe the dsPIC30F2020 device and Figure 1-3 and Table 1-3 describe the dsPIC30F2023 SMPS device. Preliminary DS70178C-page 9 ...

Page 12

... C™ Module SMPS UART1 PWM Preliminary SFLT2/INT0/OCFLTA/RA9 PORTA AN0/CMP1A/CN2/RB0 AN1/CMP1B/CN3/RB1 AN2/CMP1C/CMP2A/CN4/RB2 AN3/CMP1D/CMP2B/CN5/RB3 AN4/CMP2C/CN6/RB4 AN5/CMP2D/CN7/RB5 OSC1/CLKI/RB6 OSC2/CLKO/RB7 PORTB PGC2/EMUC2/OC1/SFLT1/ INT1/RD0 PORTD PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 RE4 RE5 PGC1/EMUC1/EXTREF/T1CK/ U1ARX/CN0/RE6 PGD1/EMUD1/T2CK/U1ATX/ CN1/RE7 PORTE PGD2/EMUD2/SCK1/SFLT3/ INT2/RF6 PGC/EMUC/SDI1/SDA/U1RX/RF7 PGD/EMUD/SD01/SCL/U1TX/RF8 PORTF © 2006 Microchip Technology Inc. ...

Page 13

... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. dsPIC30F1010/202X Description Analog input channels. Positive supply for analog module. Ground reference for analog module. External clock source input. Always associated with OSC1 pin function. ...

Page 14

... Can be software programmed for internal weak pull-ups on all inputs. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. External reference to Comparator DAC Analog = O P Preliminary 2 C™ Analog input = Output = Power © 2006 Microchip Technology Inc. ...

Page 15

... FIGURE 1-2: dsPIC30F2020 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Address Latch Control Control Logic Logic Program Memory (12 Kbytes) 16 Data Latch ROM Latch Instruction Decode & Control Control Signals ...

Page 16

... Table 1-2 provides a brief description of device I/O pinouts for the dsPIC30F2020 and the functions that may be multiplexed to a port pin. Multiple functions may exist on one port pin. When multiplexing occurs, the peripheral module’s functional requirements may force an override of the data direction of the port pin. ...

Page 17

... TABLE 1-2: PINOUT I/O DESCRIPTIONS FOR dsPIC30F2020 (CONTINUED) Pin Buffer Pin Name Type Type RB0-RB7 I/O ST RA9 I/O ST RD0 I/O ST RE0-RE7 I/O ST RF6, RF7, RF8 I/O ST SCK1 I/O ST SDI1 I ST SDO1 O — SCL I/O ST SDA I/O ST T1CK I ST T2CK I ST U1RX ...

Page 18

... AN5/CMP2D/CMP3B/CN7/RB5 AN6/CMP3C/CMP4A/ OSC1/CLKI/RB6 AN7/CMP3D/CMP4B/ OSC2/CLKO/RB7 AN8/CMP4C/RB8 AN9/EXTREF/CMP4D/RB9 AN10/IFLT4/RB10 AN11/IFLT2/RB11 PORTB PGC2/EMUC2/OC1/IC1/INT1/ RD0 OC2/RD1 PORTD PWM1L/RE0 PWM1H/RE1 PWM2L/RE2 PWM2H/RE3 PWM3L/RE4 PWM3H/RE5 PGC1/EMUC1/PWM4L/T1CK/ U1ARX/CN0/RE6 PGD1/EMUD1/PWM4H/T2CK/ U1ATX/CN1/RE7 PORTE U1RX/RF2 U1TX/RF3 PGD2/EMUD2/SCK1/INT2/RF6 PGC/EMUC/SDI1/RF7 PGD/EMUD/SD01/RF8 SYNCI/RF14 SYNCO/SSI/RF15 PORTF SCL/RG2 SDA/RG3 PORTG © 2006 Microchip Technology Inc. ...

Page 19

... CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. dsPIC30F1010/202X Description Analog input channels. Positive supply for analog module. Ground reference for analog module. External clock source input. Always associated with OSC1 pin function. ...

Page 20

... Input Change notification inputs Can be software programmed for internal weak pull-ups on all inputs. Positive supply for logic and I/O pins. Ground reference for logic and I/O pins. External reference to Comparator DAC Analog O P Preliminary Analog input = Output = Power © 2006 Microchip Technology Inc. ...

Page 21

... Moreover, only the lower 16 bits of each instruction word can be accessed using this method. © 2006 Microchip Technology Inc. dsPIC30F1010/202X • Linear indirect access of 32K word pages within program space is also possible using any working register, via table read and write instructions ...

Page 22

... The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address instruction words. Preliminary © 2006 Microchip Technology Inc. ...

Page 23

... DSP ACCA Accumulators ACCB PC22 7 0 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2006 Microchip Technology Inc. dsPIC30F1010/202X D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 ...

Page 24

... Note: The Divide flow is interruptible. However, the user needs to save the context as appropriate. Function Signed fractional divide: Wm/Wn W0; Rem Signed divide: (Wm + 1:Wm)/Wn W0; Rem Unsigned divide: (Wm + 1:Wm)/Wn Signed divide W0; Rem Unsigned divide W0; Rem Preliminary W1 W1 W0; Rem © 2006 Microchip Technology Inc. ...

Page 25

... ED EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2006 Microchip Technology Inc. dsPIC30F1010/202X The DSP engine has various options selected through various bits in the CPU Core Configuration Register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...

Page 26

... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70178C-page 24 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2006 Microchip Technology Inc. ...

Page 27

... B) as its pre- accumulation source and post-accumulation destina- tion. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 2.4.2.1 Adder/Subtracter, Overflow and Saturation ...

Page 28

... Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary © 2006 Microchip Technology Inc. ...

Page 29

... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 15-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...

Page 30

... NOTES: DS70178C-page 28 Preliminary © 2006 Microchip Technology Inc. ...

Page 31

... Configuration bits. Otherwise, bit 23 is always clear. Note: The address map shown in Figure 3-1 is conceptual, and the actual memory con- figuration may vary across individual devices depending on available memory. © 2006 Microchip Technology Inc. dsPIC30F1010/202X FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR dsPIC30F1010/ 202X GOTO Reset – ...

Page 32

... Note: Program Space Visibility cannot be used to access bits <23:16> word in program memory. DS70178C-page 30 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> 0 PSVPAG<7:0> 23 bits Program Counter Select bits 15 bits EA 8 bits 16 bits 24-bit EA Preliminary <15> <14:1> <0> PC<22:1> 0 Data EA <15:0> Data EA <15:0> Data EA <14:0> 0 Byte Select © 2006 Microchip Technology Inc. ...

Page 33

... Program Memory ‘Phantom’ Byte (Read as ‘0’). © 2006 Microchip Technology Inc. dsPIC30F1010/202X A set of Table Instructions is provided to move byte or word sized data to and from program space. 1. TBLRDL: Table Read Low Word: Read the lsw of the program address; ...

Page 34

... Execution prior to exiting the loop due to an interrupt - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle. Preliminary 8 0 © 2006 Microchip Technology Inc. ...

Page 35

... The data space memory is split into two blocks, X and Y data space. A key element of this architecture is that Y space is a subset of X space, and is fully contained within X space. In order to provide an apparent linear addressing space, X and Y spaces have contiguous addresses. © 2006 Microchip Technology Inc. dsPIC30F1010/202X Program Space 0x0000 (1) PSVPAG ...

Page 36

... DS70178C-page 34 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 256 bytes 0x08FE 0x0900 Y Data RAM (Y) 256 bytes 0x09FE 0x0A00 (See Note) 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary LSB 2560 bytes Near Data Space © 2006 Microchip Technology Inc. ...

Page 37

... FIGURE 3-7: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2006 Microchip Technology Inc. dsPIC30F1010/202X SFR SPACE UNUSED Y SPACE UNUSED MAC Class Ops Read-Only Indirect EA using W10, W11 ...

Page 38

... FIGURE 3-8: 15 Byte 1 0001 0x0000 Byte 3 0003 0x0000 Byte 5 0005 0x0000 Preliminary ® DATA ALIGNMENT MSB LSB Byte 0 0000 Byte 2 0002 Byte 4 0004 © 2006 Microchip Technology Inc. ...

Page 39

... Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> is forced to ‘0’, because all stack operations must be word-aligned. Whenever an Effective Address (EA) is © 2006 Microchip Technology Inc. dsPIC30F1010/202X generated using W15 as a source or destination pointer, the address thus generated is compared with the value in SPLIM ...

Page 40

TABLE 3-3: CORE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 0016 ...

Page 41

TABLE 3-3: CORE REGISTER MAP (CONTINUED) SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 MODCON 0046 XMODEN YMODEN — — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — BSRAM 0750 ...

Page 42

... NOTES: DS70178C-page 40 Preliminary © 2006 Microchip Technology Inc. ...

Page 43

... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2006 Microchip Technology Inc. dsPIC30F1010/202X 4.1 Instruction Addressing Modes The Addressing modes in Table 4-1 form the basis of the Addressing modes optimized to support the specific features of individual instructions ...

Page 44

... DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode source and itself. Certain operations, such as NOP, do not have any operands. Preliminary © 2006 Microchip Technology Inc. ...

Page 45

... Bidirectional mode, (i.e., address bound- ary checks will be performed on both the lower and upper address boundaries). © 2006 Microchip Technology Inc. dsPIC30F1010/202X 4.2.1 START AND END ADDRESS The modulo addressing scheme requires that a ...

Page 46

... W1, X AGU for modulo MOV #0x0000,W0 ;W0 holds buffer fill value MOV #0x1110,W1 ;point W1 to buffer DO AGAIN,#0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0,W0 ;increment the fill value Preliminary © 2006 Microchip Technology Inc. ...

Page 47

... BIT-REVERSED ADDRESS EXAMPLE b15 b14 b13 b12 b11 b10 b9 b8 b15 b14 b13 b12 b11 b10 b9 b8 © 2006 Microchip Technology Inc. dsPIC30F1010/202X If the length of a bit-reversed buffer then the last ‘N’ bits of the data buffer start address must be zeros. ...

Page 48

... Modifier values greater than 256 words exceed the data memory available on the dsPIC30F1010/202X device DS70178C-page 46 Decimal XB<14:0> Bit-Reversed Address Modifier Value Preliminary Bit-Reversed Address A0 Decimal (1) 0x4000 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 © 2006 Microchip Technology Inc. ...

Page 49

... The INTCON2 register controls the external inter- rupt request signal behavior and the use of the alternate vector table. © 2006 Microchip Technology Inc. dsPIC30F1010/202X • The INTTREG register contains the associated interrupt vector number and the new CPU inter- rupt priority level, which are latched into vector number (VECNUM< ...

Page 50

... ADC Pair 3 Conversion Done 41 49 ADC Pair 4 Conversion Done 42 50 ADC Pair 5 Conversion Done 43 51 Reserved 44 52 Reserved 45-53 53-61 Reserved Lowest Natural Order Priority Preliminary © 2006 Microchip Technology Inc. Interrupt Source 2 C™ Slave Event 2 C Master Event ...

Page 51

... Trap Lockout: Occurrence of multiple Trap conditions simultaneously will cause a Reset. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 5.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 5-1 ...

Page 52

... Stack Error Trap Vector Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector Interrupt 1 Vector Interrupt 52 Vector Interrupt 53 Vector Preliminary © 2006 Microchip Technology Inc. 0x000000 0x000002 0x000004 0x000014 — — — 0x00007E 0x000080 0x000082 0x000084 0x000094 — ...

Page 53

... The RETFIE (Return from Interrupt) instruction will unstack the Program Counter and status registers to return the processor to its state prior to the interrupt sequence. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 5.5 Alternate Vector Table In Program Memory, the IVT is followed by the AIVT, as shown in Figure 5-1 ...

Page 54

... Address error trap has not occurred DS70178C-page 52 R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE R/W-0 R/W-0 R/W-0 MATHERR ADDRERR STKERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OVBTE COVTE bit 8 R/W-0 U-0 OSCFAIL — bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 55

... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary DS70178C-page 53 ...

Page 56

... Interrupt on positive edge DS70178C-page 54 U-0 U-0 U-0 — — — U-0 U-0 R/W-0 — — INT2EP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 R/W-0 INT1EP INT0EP bit Bit is unknown ...

Page 57

... Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 Unimplemented: Read as ‘0’ bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 NVMIF ADIF U1TXIF ...

Page 58

... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70178C-page 56 Preliminary © 2006 Microchip Technology Inc. ...

Page 59

... INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 R/W-0 U-0 — CNIF — ...

Page 60

... Interrupt request has not occurred DS70178C-page 58 U-0 U-0 R/W-0 — — ADCP5IF U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R/W-00 R/W-0 ADCP4IF ADCP3IF bit 8 U-0 R/W-0 — AC4IF bit Bit is unknown ...

Page 61

... OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4 Unimplemented: Read as ‘0’ bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 NVMIE ADIE U1TXIE U-0 ...

Page 62

... Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70178C-page 60 Preliminary © 2006 Microchip Technology Inc. ...

Page 63

... Interrupt request not enabled bit 1 INT2IE: External Interrupt 2 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 R/W-0 U-0 — CNIE — R/W-0 ...

Page 64

... Interrupt request not enabled DS70178C-page 62 U-0 U-0 R/W-0 — — ADCP5IE U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R/W-0 R/W-0 ADCP4IE ADCP3IE bit 8 U-0 R/W-0 — AC4IE bit Bit is unknown ...

Page 65

... Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 66

... Unimplemented: Read as ‘0’ DS70178C-page 64 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 T2IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 67

... Unimplemented: Read as ‘0’ bit 2-0 SPI1IP<2:0>: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 68

... Interrupt is priority 1 000 = Interrupt source is disabled DS70178C-page 66 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 MI2CIP<2:0> bit 8 R/W-0 R/W-0 NVMIP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 69

... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...

Page 70

... Interrupt is priority 1 000 = Interrupt source is disabled DS70178C-page 68 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 PWM4IP<2:0> bit 8 R/W-0 R/W-0 PWM2IP<2:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 71

... CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 U-0 U-0 — — U-0 U-0 U-0 — ...

Page 72

... Unimplemented: Read as ‘0’ DS70178C-page 70 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 AC2IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 73

... Unimplemented: Read as ‘0’ bit 2-0 AC4IP<2:0>: Analog Comparator 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 U-0 — — — U-0 ...

Page 74

... Unimplemented: Read as ‘0’ DS70178C-page 72 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 ADCP1IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 75

... Unimplemented: Read as ‘0’ bit 2-0 ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...

Page 76

... Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70178C-page 74 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2006 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...

Page 77

TABLE 5-2: INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Name INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 ALTIVT DISI — — 0082 IFS0 0084 — MI2CIF SI2CIF NVMIF IFS1 0086 AC3IF AC2IF ...

Page 78

... NOTES: DS70178C-page 76 Preliminary © 2006 Microchip Technology Inc. ...

Page 79

... WR LAT + WR Port Data Latch Read LAT Read Port © 2006 Microchip Technology Inc. dsPIC30F1010/202X is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx), read the latch. Writes to the latch, write the latch (LATx). Reads from the port (PORTx), read the port pins, and writes to the port pins, write the latch (LATx) ...

Page 80

... PUE) bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. Preliminary © 2006 Microchip Technology Inc. ...

Page 81

TABLE 6-1: dsPIC30F1010/2020 PORT REGISTER MAP Bit SFR Name Addr. Bit 15 Bit 14 Bit 13 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — TRISB 02C6 — — — ...

Page 82

TABLE 6-2: dsPIC30F2023 PORT REGISTER MAP SFR Bit Addr. Bit 15 Bit 14 Bit 13 Name 12 TRISA 02C0 — — — — TRISA11 TRISA10 PORTA 02C2 — — — — LATA 02C4 — — — — LATA11 TRISB 02C6 ...

Page 83

... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. dsPIC30F1010/202X 7.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory 32 instructions (96 bytes time and can write program memory data 32 instructions (96 bytes time ...

Page 84

... NVMKEY register. Refer to Section 7.6 DD “Programming Operations” for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Preliminary © 2006 Microchip Technology Inc. ...

Page 85

... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2006 Microchip Technology Inc. dsPIC30F1010/202X 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program and set WREN bit. ...

Page 86

... Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2006 Microchip Technology Inc. ...

Page 87

TABLE 7-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend uninitialized bit Note: Refer ...

Page 88

... NOTES: DS70178C-page 86 Preliminary © 2006 Microchip Technology Inc. ...

Page 89

... These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 8-1 presents a block diagram of the 16-bit timer module. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 16-bit Timer Mode: In the 16-bit Timer mode, the timer increments on every instruction cycle match value, preloaded into the period register PR1, then resets to 0 and continues to count ...

Page 90

... When a match between the timer and the period regis- ter occurs, an interrupt can be generated, if the respective timer interrupt enable bit is asserted. TCKPS<1:0> Preliminary TSYNC Sync 1 0 TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2006 Microchip Technology Inc. ...

Page 91

... Enabling an interrupt is accomplished via the respec- tive timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 control register in the Interrupt Controller. © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary DS70178C-page 89 ...

Page 92

TABLE 8-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) ...

Page 93

... Interrupt on a 32-bit Period Register Match These operating modes are determined by setting the appropriate bit(s) in the 16-bit T2CON and T3CON SFRs. © 2006 Microchip Technology Inc. dsPIC30F1010/202X For 32-bit timer/counter operation, Timer2 is the least significant word and Timer3 is the most significant word of the 32-bit timer ...

Page 94

... Timer Configuration bit T32, (T2CON<3>) must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. DS70178C-page 92 16 TMR2 Sync LSB PR2 Q D TGATE(T2CON<6> TON 1 X Gate 0 1 Sync Preliminary TCKPS<1:0> 2 Prescaler 1, 8, 64, 256 © 2006 Microchip Technology Inc. ...

Page 95

... T3IF Event Flag 1 TGATE Note: The dsPIC30F202X does not have an external pin input to TIMER3. The following modes should not be used: 1. TCS = 1 2. TCS = 0 and TGATE = 1 (gated time accumulation) © 2006 Microchip Technology Inc. dsPIC30F1010/202X PR2 Comparator x 16 TMR2 Q D TGATE Q CK ...

Page 96

... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). Preliminary © 2006 Microchip Technology Inc. ...

Page 97

TABLE 9-1: TIMER2/3 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...

Page 98

... NOTES: DS70178C-page 96 Preliminary © 2006 Microchip Technology Inc. ...

Page 99

... ICxCON Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channels 1 through N. © 2006 Microchip Technology Inc. dsPIC30F1010/202X The key operational features of the Input Capture module are: • Simple Capture Event mode • Timer2 and Timer3 mode selection • ...

Page 100

... The input capture interrupt flag is set on every edge, rising and falling. • The Interrupt on Capture mode setting bits, ICI<1:0>, are ignored, since every capture generates an interrupt. • A Capture Overflow condition is not generated in this mode. Preliminary © 2006 Microchip Technology Inc. ...

Page 101

... Sleep mode. The prescale settings of 4:1 or 16:1 are not applicable in this mode. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 10.2.2 INPUT CAPTURE IN CPU IDLE ...

Page 102

TABLE 10-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — Legend uninitialized bit Note: Refer to the “dsPIC30F Family Reference Manual” (DS70046) for ...

Page 103

... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 and 2. © 2006 Microchip Technology Inc. dsPIC30F1010/202X The key operational features of the Output Compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...

Page 104

... Set the PWM period by writing to the appropriate period register. 2. Set the PWM duty cycle by writing to the OCxRS register. 3. Configure the output compare module for PWM operation. 4. Set the TMRx prescale value and enable the Timer, TON (TxCON<15> Preliminary . © 2006 Microchip Technology Inc. ...

Page 105

... Fault condition has been removed, and the PWM mode is reenabled by writing the appropriate mode bits, OCM<2:0> in the OCxCON register. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 11.5 Output Compare Operation During CPU Sleep Mode When the CPU enters the Sleep mode, all internal clocks are stopped ...

Page 106

... T3IE), located in the IEC0 Control register. The output com- pare interrupt flag is never set during the PWM mode of operation. DS70178C-page 104 Period TMR3 = PR3 T3IF = 1 (Interrupt Flag) OCxR = OCxRS TMR3 = Duty Cycle (OCxR) Preliminary © 2006 Microchip Technology Inc. ...

Page 107

TABLE 11-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — Note: Refer to ...

Page 108

... NOTES: DS70178C-page 106 Preliminary © 2006 Microchip Technology Inc. ...

Page 109

... PWM output pins: PWM1H, PWM1L, PWM2H, PWM2L, PWM3H, PWM3L, PWM4H and PWM4L. For complementary outputs, these eight I/O pins are grouped into H/L pairs. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.2 Description The PWM module is designed for applications that ...

Page 110

... Dead-time Generator Channel 4 Dead-time Generator External Time Base Synchronization Special Event Special Event Trigger Postscaler Fault mode and pin control Preliminary PWM1H PWM1L PWM2H PWM2L PWM3H PWM3L PWM4H PWM4L Fault Control SFLT X Logic IFLT X SYNCO SYNCI © 2006 Microchip Technology Inc. ...

Page 111

... TRGCONx: PWM TRIGGER Control Register • IOCONx: PWM I/O Control Register • FCLCONx: PWM Fault Current-Limit Control Register • TRIGx: PWM Trigger Compare Value Register • LEBCONx: Leading Edge Blanking Control Register © 2006 Microchip Technology Inc. dsPIC30F1010/202X TMR < PDC Dead PWM Override ...

Page 112

... Postscale DS70178C-page 110 R/W-0 R/W-0 R/W-0 SESTAT SEIEN EIPU R/W-0 R/W-0 R/W-0 SEVTPS<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SYNCPOL SYNCOEN bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 113

... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-3 Special Event Compare Count Value bits bit 2-0 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 PTPER <15:8> R/W-0 R/W-0 U-0 — ...

Page 114

... U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 ITB MDCS bit 8 R/W-0 R/W-0 XPRES IUE bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 115

... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 PWM Generator #x Duty Cycle Value bits Note 1: The minimum value for this register is 0x0008 and the maximum value is 0xFFEF. © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 PDCx<15:8> R/W-0 R/W-0 R/W-0 PDCx< ...

Page 116

... R/W-0 DTRx<7:2> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 R/W-0 bit 8 R/W-0 U-0 U-0 — — bit Bit is unknown R/W-0 R/W-0 R/W-0 bit 8 R/W-0 U-0 U-0 — — bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 117

... Unimplemented: Read as ‘0’ bit 5-0 TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits This value specifies the ROLL counter value needed for a match that will then enable the trigger postscaler logic to begin counting trigger events. © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 ALTDTRx< ...

Page 118

... Output overrides via the OVDDAT<1:0> bits occur on next clock boundary DS70178C-page 116 R/W-0 R/W-0 R/W-0 POLL PMOD<1:0> R/W-0 R/W-0 R/W-0 CLDAT<1:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OVRENH OVRENL bit 8 U-0 R/W-0 — OSYNC bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 119

... CLPOL: Current-Limit Polarity for PWM Generator #X bit 1 = The selected current-limit source is low active 0 = The selected current-limit source is high active bit 7 CLMODE: Current-Limit Mode Enable for PWM Generator #X bit 1 = Current-limit function is enabled 0 = Current-limit function is disabled © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 CLSRC<3:0> R/W-0 ...

Page 120

... FLTMOD<1:0>: Fault Mode for PWM Generator #x bits 00 = The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (latched condition The selected Fault source forces PWMxH, PWMxL pins to FLTDAT values (cycle Reserved 11 = Fault input is disabled DS70178C-page 118 Preliminary © 2006 Microchip Technology Inc. ...

Page 121

... The minimum usable value for this register is 0x0008 A value of 0x0000 does not produce a trigger. If the TRIGx value is being calculated based on duty cycle value, you must ensure that a minimum TRIGx value is written into the register at all times. © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 TRGCMP< ...

Page 122

... Unimplemented: Read as ‘0’ DS70178C-page 120 R/W-0 R/W-0 R/W-0 PLF FLTLEBEN CLLEBEN R/W-0 R/W-0 U-0 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 LEB<9:8> bit 8 U-0 U-0 — — bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 123

... Value Timer Value 0 PWMH Duty Cycle Period © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.4.2 COMPLEMENTARY PWM MODE Complementary PWM is generated in a manner similar to standard Edge-Aligned PWM. Complementary mode provides a second PWM output signal on the PWML pin that is the complement of the primary PWM signal (PWMH) ...

Page 124

... PWM mode. FIGURE 12-8: CYCLE-BY-CYCLE CURRENT-LIMIT PWM MODE FLTx Negates PWM Period Value Duty Cycle Timer Value 0 PWMH Programmed Duty Cycle PWMH Actual Duty Cycle Preliminary © 2006 Microchip Technology Inc. Current-Limit FLTx Negates PWM Programmed Duty Cycle Actual Duty Cycle ...

Page 125

... PWMH Duty Cycle Duty Cycle Actual Period Programmed Period © 2006 Microchip Technology Inc. dsPIC30F1010/202X Typically, in the converter application, an energy stor- age inductor is charged with current while the PWM signal is asserted, and the inductor current is dis- charged by the load when the PWM signal is deas- serted ...

Page 126

... PWM signals. The user may initialize these individual time base counters before or during operation via the phase-shift registers. The primary (PTMR) and the individual timers (TMRx) are not user readable. Preliminary © 2006 Microchip Technology Inc. ...

Page 127

... PWM time base. The timer period can be updated at any time by the user. The PWM period can be determined from the following formula: Period Duration = (PTPER + 1)/120 MHz @ 30 MIPS © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.9 PWM Frequency and Duty Cycle Resolution 3 The PWM Duty cycle resolution is 1 ...

Page 128

... The user is responsible for limiting the duty cycle values to the allowable range of 0x0008 to 0xFFEF. Note: A duty cycle of 0x0000 will produce a zero PWM output, and a 0xFFFF duty cycle value will produce a high on the PWM output. PWMx signal 0 Preliminary © 2006 Microchip Technology Inc. ...

Page 129

... DTC<1:0> bit in the PWMCON register FIGURE 12-15: DEAD-TIME INSERTION FOR COMPLEMENTARY PWM t da PWM Generator #1 Output PWM1H PWM1L © 2006 Microchip Technology Inc. dsPIC30F1010/202X FIGURE 12-16: DTR1 ALTDR1 PWM1 in DTR2 ALTDTR2 PWM2 in DTR3 ALTDTR3 PWM3 in DTR4 ...

Page 130

... Preliminary EXAMPLE DEAD-TIME RANGES Dead-Time Range 4.16 ns 0-17.03 µsec 6.25 ns 0-25.59 µsec CLOCK 8 PTMR DEAD-TIME VALUE <10:4> DUTY CYCLE REG <15:4> RAW PWMH RAW PWML PWMH OUTPUT PWML OUTPUT © 2006 Microchip Technology Inc. ...

Page 131

... PTCON) to control its operation. The PTMR value that causes a Special Event Trigger is loaded into the SEVTCMP register. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.17.1 SPECIAL EVENT TRIGGER ENABLE The PWM module always produces Special Event Trig- ger pulses. This signal can optionally be used by the ADC module ...

Page 132

... Dead time ~ 67nsec ; Hex(40) = decimal(64) ; So, Dead time = 64*1.05nsec = 67.2nsec ; Note that the last 2 bits are unimplemented, ; therefore the dead time register can achieve resolution of about 4nsec. ; Load the same value in ALTDTR1 register ; turn ON PWM module Preliminary © 2006 Microchip Technology Inc. ...

Page 133

... The primary time base special event interrupt is enabled via the SEIEN bit in the PTCON register. The individual time base interrupts generated by the trigger logic in each PWM generator are controlled by the TRGIEN bit in the PWMCONx registers. © 2006 Microchip Technology Inc. dsPIC30F1010/202X PDI 15 3 ...

Page 134

... FLTMOD<1:0> ‘1011’ FLTMOD<1:0> – FLTSTAT signal is latched until Reset in software ‘1101’ FLTMOD<1:0> – FLTSTAT signal is Reset by PTMR every PWM cycle FLTMOD<1:0> – FLTSTAT signal is disabled ‘1111’ FLTSRC<3:0> Preliminary PWMxH,L MUX 2 1 FLTSTAT © 2006 Microchip Technology Inc. ...

Page 135

... PWM outputs return to normal operation at the beginning of the following PWM cycle. The operating mode for each Fault input pin is selected using the FLTMOD<1:0> control bits in the FCLCONx register. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.23.4 FAULT ENTRY The response of the PWM pins to the Fault input pins is always asynchronous with respect to the device clock signals ...

Page 136

... Fault pins in software. PWMxH,L Signals PWM Period Reset EN CLDAT<1:0> CLMOD XPRES EN ‘0000’ ‘0001’ ‘0010’ ‘0011’ MUX ‘1000’ ‘1001’ ‘1010’ ‘1011’ ‘1101’ ‘1111’ CLSRC<3:0> Preliminary PWMxH,L MUX 2 1 CLSTAT © 2006 Microchip Technology Inc. ...

Page 137

... If the CLDAT or FLTDAT bits are set to ‘1’, and their associated event occurs, then these asserted outputs will be delayed by clocked logic in the dead-time circuitry. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.29 Asserting Outputs via Current Limit It is possible to use the CLDAT bits to assert the PWMxH,L outputs in response to a current-limit event. Such behavior could be used as a current “ ...

Page 138

... MIPS operation. Unused portions of reg- isters always read as zeros. The use of data alignment makes it easier to write soft- ware because it eliminates the need to shift time values to fit into registers. It also eases the computation and understanding of time allotment within a PWM cycle. Preliminary © 2006 Microchip Technology Inc. ...

Page 139

... IN PWM1H Boost Converter PWM1H © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.34.2 APPLICATION OF COMPLEMENTARY PWM MODE Complementary mode PWM is often used in circuits that use two transistors in a bridge configuration where transformers are not used, as shown in Figure 12-23. If transformers are used, then some means must be provided to ensure that no net DC currents flow through the transformer to prevent core saturation ...

Page 140

... FIGURE 12-25: T OFF PWM1H PWM1L Dead Time PWM2H PWM2L L1 V OUT PWM3H + PWM3L + V IN PWM1H PWM2H L1 V OUT + PWM1L PWM1L L1 V OUT + Preliminary APPLICATIONS OF MULTI- PHASE PWM MODE Multiphase DC/DC Converter PWM3H V OUT PWM1L © 2006 Microchip Technology Inc. ...

Page 141

... Full Bridge ZVT Converter PWM1H T1 PWM1H PWM1H PWM1H © 2006 Microchip Technology Inc. dsPIC30F1010/202X 12.34.6 APPLICATION OF CURRENT RESET PWM MODE In Current Reset PWM mode, the PWM frequency var- ies with the load current. This mode is different than most PWM modes because the user sets the maxi- mum PWM period, but an external circuit measures the inductor current ...

Page 142

... INDEPENDENT PWM CHANNEL DITHERING ISSUES: Issues for multi-phase or variable phase designs using independent output dithering must consider these issues: 1. The phases are no longer phase aligned. 2. Control of current sharing among phases is more difficult. Preliminary © 2006 Microchip Technology Inc. ...

Page 143

... Assume further that each PWM generator is operating at 1000 kHz (1 µsec period) and each control loop is operating at 125 kHz (8 µsec). © 2006 Microchip Technology Inc. dsPIC30F1010/202X The TRGDIV<2:0> bits in each TRGCONx register will be set to ‘111’, which selects that every 8th trigger comparison match will generate a trigger signal to the ADC to capture data and begin a conversion process ...

Page 144

TABLE 12-4: POWER SUPPLY PWM REGISTER MAP File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 PTCON 0400 PTEN — PTSIDL SESTAT PTPER 0402 MDC 0404 SEVTCMP 0406 PWMCON1 0408 FLTSTAT CLSTAT TRGSTAT FLTIEN IOCON1 040A PENH PENL ...

Page 145

TABLE 12-4: POWER SUPPLY PWM REGISTER MAP (CONTINUED) File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 FCLCON4 0448 — — — PDC4 044A PHASE4 044C DTR4 044E — — ALTDTR4 0450 — — TRIG4 0452 TRGCON4 0454 ...

Page 146

... NOTES: DS70178C-page 144 Preliminary © 2006 Microchip Technology Inc. ...

Page 147

... If any transmit data has been written to the buffer register, the contents © 2006 Microchip Technology Inc. dsPIC30F1010/202X of the transmit buffer are moved to SPIxSR. The received data is thus placed in SPIxBUF and the transmit data in SPIxSR is ready for the next transfer ...

Page 148

... These features are available on the dsPIC30F2023. DS70178C-page 146 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus Preliminary 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2006 Microchip Technology Inc. ...

Page 149

... FIGURE 13-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM dsPIC33F (SPI Slave, Frame Slave) FIGURE 13-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F (SPI Master, Frame Slave) © 2006 Microchip Technology Inc. dsPIC30F1010/202X PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx ...

Page 150

... Preliminary 4:1 6:1 8:1 7500 5000 3750 1875 1250 937.5 469 312.5 234.4 117 78.1 58.6 1250 833 625 313 208 156 © 2006 Microchip Technology Inc. ...

Page 151

... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 U-0 — ...

Page 152

... SPI modes (FRMEN = 1). DS70178C-page 150 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 153

... FRMDLY: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 Unimplemented: This bit must not be set to ‘1’ by the user application. © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 U-0 — ...

Page 154

TABLE 13-2: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name SPI1STAT 0240 SPIEN — SPISIDL — SPI1CON 0242 — — — DISSCK DISSDO MODE16 SPI1CON2 0244 FRMEN SPIFSD FRMPOL — SPI1BUF 0246 Legend: u ...

Page 155

... I2CRCV is the receive buffer, as shown in Figure 16-1. I2CTRN is the transmit register to which bytes are writ- ten during a transmit operation, as shown in Figure 16-2. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 14.1 Operating Function Description ...

Page 156

... Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Preliminary Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2006 Microchip Technology Inc. ...

Page 157

... SCL. After 8 bits are received, if I2CRCV is not full or I2COV is not set, I2CRSR is transferred to I2CRCV. ACK is sent on the ninth clock. © 2006 Microchip Technology Inc. dsPIC30F1010/202X If the RBF flag is set, indicating that I2CRCV is still holding data from a previous operation (RBF = 1), then ACK is not sent ...

Page 158

... C module generates two interrupt flags, MI2CIF Master Interrupt Flag) and SI2CIF (I rupt Flag). The MI2CIF interrupt flag is activated on completion of a master message event. The SI2CIF interrupt flag is activated on detection of a message directed to the slave. Preliminary © 2006 Microchip Technology Inc Slave Inter- ...

Page 159

... Generate a Stop condition on SDA and SCL. 2 • Configure the I C port to receive data. • Generate an ACK condition at the end of a received byte of data. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 2 14. Master Operation The master device generates all of the serial clock pulses and the Start and Stop conditions ...

Page 160

... C OPERATION DURING CPU IDLE MODE 2 For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Preliminary 2 C bus © 2006 Microchip Technology Inc. ...

Page 161

TABLE 14-1: I C™ REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name — — — — I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — I2CCON 0206 I2CEN ...

Page 162

... NOTES: DS70178C-page 160 Preliminary © 2006 Microchip Technology Inc. ...

Page 163

... Prescaler FIGURE 15-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator UART1 Receiver UART1 Transmitter © 2006 Microchip Technology Inc. dsPIC30F1010/202X • Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS • 4-Deep First-In-First-Out (FIFO) Transmit Data Buffer • 4-Deep FIFO Receive Data Buffer • ...

Page 164

... BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. Preliminary /(16 * 65536). UART BAUD RATE WITH (1,2,3) BRGH = • (U1BRG + – • Baud Rate denotes the instruction cycle clock is 7.5 MHz MHz (1) © 2006 Microchip Technology Inc. ...

Page 165

... TSR. Serial bit stream will start shifting out with the first rising edge of the baud clock transmit interrupt will be generated as per the setting of control bit, UTXISELx. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 15.4 Break and Sync Transmit Sequence The following sequence will send a message frame header made Break, followed by an auto-baud Sync byte ...

Page 166

... BRG generates 16 clocks per bit period (16x Baud Clock, Standard mode) DS70178C-page 164 R/W-0 U-0 R/W-0 IREN — ALTIO R/W-0 R/W-0 R/W-0 RXINV BRGH PDSEL1 HC = Hardware Cleared ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 PDSEL0 STSEL bit Hardware Select x = Bit is unknown © 2006 Microchip Technology Inc. ...

Page 167

... PDSEL1:PDSEL0: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary DS70178C-page 165 ...

Page 168

... Address Detect mode disabled DS70178C-page 166 U-0 R/W-0 R/W-0 — UTXBRK UTXEN R/W-0 R/W-0 R/W-0 RIDLE PERR FERR HS =Hardware Set ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 UTXBF TRMT bit 8 R/W-0 R/W-0 OERR URXDA bit Hardware Cleared x = Bit is unknown © 2006 Microchip Technology Inc. ...

Page 169

... RSR to the empty state) bit 0 URXDA: Receive Buffer Data Available bit (Read-Only Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty © 2006 Microchip Technology Inc. dsPIC30F1010/202X Preliminary 0 transition) will reset DS70178C-page 167 ...

Page 170

TABLE 15-1: UART1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr U1MODE 0220 UARTEN — USIDL IREN U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — U1TXREG 0224 — — — — U1RXREG 0226 — — — ...

Page 171

... PWM output to the applica- tion circuit. The very high speed operation of this ADC module allows “data on demand”. © 2006 Microchip Technology Inc. dsPIC30F1010/202X In addition, several hardware features have been added to the peripheral interface to improve real-time performance in a typical DSP based application ...

Page 172

... AN10 AN1 AN3 AN11 DS70178C-page 170 Dedicated Sample & Holds 10-Bit SAR DAC AV DD Even numbered inputs without dedicated Sample and Hold Common Sample and Hold Preliminary 12-word, 16-bit Registers Conversion Logic Comparator AV SS MUX/Sample/Sequence Control © 2006 Microchip Technology Inc. ...

Page 173

... If the shared S&H is busy at the time the dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion cycle bit 4-3 Unimplemented: Read as ‘0’ © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 — ...

Page 174

... F /10 = 1.5 MHz @ 7.5 MIPS ADC 010 = 1.87 MHz @ 7.5 MIPS ADC 001 = 2.5 MHz @ 7.5 MIPS ADC 000 = 3.75 MHz @ 7.5 MIPS ADC Note: See Figure 18-2 for ADC clock derivation. DS70178C-page 172 Preliminary © 2006 Microchip Technology Inc. ...

Page 175

... Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. bit 0 P0RDY: Conversion Data for Pair #0 Ready bit Bit set when data is ready in buffer, cleared when a ‘0’ is written to this bit. © 2006 Microchip Technology Inc. dsPIC30F1010/202X U-0 U-0 U-0 — ...

Page 176

... R/W-0 R/W-0 PCFG4 PCFG3 PCFG2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 U-0 — bit Bit is unknown R/W-0 R/W-0 PCFG9 PCFG8 bit 8 R/W-0 R/W-0 PCFG1 PCFG0 bit Bit is unknown SS © 2006 Microchip Technology Inc. ...

Page 177

... SWTRG0: Software Trigger 0 bit 1 = Start conversion of AN1 and AN0 (if selected by TRGSRC bits). If other conversions are in progress, then conversion will be performed when the conversion resources are available. This bit will be reset when the PEND bit is set © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 TRGSRC1< ...

Page 178

... PWM GEN #3 current-limit ADC trigger 10001 = PWM GEN #4 current-limit ADC trigger 10110 = PWM GEN #1 fault ADC trigger 10111 = PWM GEN #2 fault ADC trigger 11000 = PWM GEN #3 fault ADC trigger 11001 = PWM GEN #4 fault ADC trigger DS70178C-page 176 Preliminary © 2006 Microchip Technology Inc. ...

Page 179

... SWTRG2: Software Trigger 2 bit 1 = Start conversion of AN5 and AN4 (if selected by TRGSRC bits). If other conversions are in progress, then conversion will be performed when the conversion resources are available. This bit will be reset when the PEND bit is set © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 TRGSRC3< ...

Page 180

... PWM GEN #3 current-limit ADC trigger 10001 = PWM GEN #4 current-limit ADC trigger 10110 = PWM GEN #1 fault ADC trigger 10111 = PWM GEN #2 fault ADC trigger 11000 = PWM GEN #3 fault ADC trigger 11001 = PWM GEN #4 fault ADC trigger DS70178C-page 178 Preliminary © 2006 Microchip Technology Inc. ...

Page 181

... SWTRG4: Software Trigger 4 bit 1 = Start conversion of AN9 and AN8 (if selected by TRGSRC bits). If other conversions are in progress, then conversion will be performed when the conversion resources are available. This bit will be reset when the PEND bit is set. © 2006 Microchip Technology Inc. dsPIC30F1010/202X R/W-0 R/W-0 R/W-0 TRGSRC5< ...

Page 182

... PWM GEN #3 current-limit ADC trigger 10001 = PWM GEN #4 current-limit ADC trigger 10110 = PWM GEN #1 fault ADC trigger 10111 = PWM GEN #2 fault ADC trigger 11000 = PWM GEN #3 fault ADC trigger 11001 = PWM GEN #4 fault ADC trigger DS70178C-page 180 Preliminary © 2006 Microchip Technology Inc. ...

Page 183

... Late sample yields zero data Measuring peak inductor current is very important © 2006 Microchip Technology Inc. dsPIC30F1010/202X 16.5 Application Information The ADC module implements a concept based on “Conversion Pairs”. In power conversion applications, there is a need to measure voltages and currents for each PWM control loop. The ADC module enables the sample and conversion process of each conversion pair to be precisely timed relative to the PWM signals ...

Page 184

... ADC will possibly have another interrupt pending. If the user clears the PxRDY bit first, the ADC may generate another interrupt request, but if the user then clears the IFS bit, the interrupt request will be erased. Preliminary © 2006 Microchip Technology Inc. ...

Page 185

... The PxRDY bit for the asso- ciated interrupt is set in the ADSTAT register at the completion of the first conversion, and remains set until it is cleared by the user. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 16.11 Conflict Resolution If more than one conversion pair request is active at the ...

Page 186

... Clear the IRQ flag in the ADC ; Actual Pair 2 Conversion Interrupt Handler ; Clear the IRQ flag in the ADC ; Actual Pair 3 Conversion Interrupt Handler ; Clear the IRQ flag in the ADC ; Actual Pair 4 Conversion Interrupt Handler Preliminary of 0x0364 (0x360 + © 2006 Microchip Technology Inc. ...

Page 187

... When operating at the maximum conversion rate of 2 Msps per channel, the sampling period is 41.6 nsec = 83.3 nsec. © 2006 Microchip Technology Inc. dsPIC30F1010/202X ; The ADC pair 0 conversion complete handler ; Restore W0-W3 and SR registers ; Return from Interrupt ...

Page 188

... The ADC module always converts pairs of analog input channels typical conversion process requires 24 clock cycles. 5th 4th 3rd 2nd 1st 10th 9th 8th 7th Preliminary 6th 5th 4th 3rd 2nd 1st © 2006 Microchip Technology Inc. ...

Page 189

... For all analog input pairs that have dedicated sample and hold circuits, the common sample and hold circuit samples the input at the start of the first conversion so that both samples (odd and even) are near simultaneous. © 2006 Microchip Technology Inc. dsPIC30F1010/202X ...

Page 190

... The A/D converts 10 bits. The data buffer RAM is 16 bits wide. The ADC data can be read in one of two dif- ferent formats, as shown in Figure 16-5. The FORM bit selects the format. Each of the output formats translates to a 16-bit result on the data bus. Preliminary © 2006 Microchip Technology Inc. OH ...

Page 191

... RAM contents: Read to Bus: Fractional d09 d08 d07 Integer © 2006 Microchip Technology Inc. dsPIC30F1010/202X d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 d06 d05 d04 d03 d02 d01 d00 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 ...

Page 192

TABLE 16-1: ADC REGISTER MAP File Name ADR Bit 15 Bit 14 Bit 13 Bit 12 ADCON 0300 ADON — ADSIDL — ADPCFG 0302 — — — — Reserved 0304 — — — — ADSTAT 0306 — — — — ...

Page 193

... Generate an interrupt • Trigger an ADC sample and convert process • Truncate the PWM signal (current limit) • Truncate the PWM period (current minimum) © 2006 Microchip Technology Inc. dsPIC30F1010/202X • Programmable output polarity • Interrupt generation capability • Selectable Input sources • ...

Page 194

... DAC output will become indeterminate. 17.9 Comparator Registers The Comparator module is controlled by the following registers: • Comparator Control Registerx (CMPCONx) • Comparator DAC Control Registerx (CMPDACx) width pulse CY Preliminary – 1 1.6) volts. An external refer- DD © 2006 Microchip Technology Inc. ...

Page 195

... CMPPOL: Comparator Output Polarity Control bit 1 = Output is inverted 0 = Output is non inverted bit 0 RANGE: Selects DAC Output Voltage Range bit 1 = High Range: Max DAC value = Low Range: Max DAC value = INTREF, 1.2V ±1% © 2006 Microchip Technology Inc. dsPIC30F1010/202X (CMPCONx) X U-0 U-0 U-0 — ...

Page 196

... DS70178C-page 194 (CMPDACx) X U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 CMREF<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2)/1024) volts depending on Range bit DD Preliminary R/W-0 R/W-0 CMREF<9:8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2006 Microchip Technology Inc. ...

Page 197

TABLE 17-1: ANALOG COMPARATOR CONTROL REGISTER MAP File Name ADR Bit 15 Bit 14 Bit 13 CMPON CMPSIDL CMPCON1 04C0 — CMPDAC1 04C2 — — — CMPON CMPSIDL CMPCON2 04C4 — CMPDAC2 04C6 — — — CMPON CMPSIDL CMPCON3 04C8 ...

Page 198

... NOTES: DS70178C-page 196 Preliminary © 2006 Microchip Technology Inc. ...

Page 199

... In the Idle mode, the clock sources are still active, but the CPU is shut off. The RC oscillator option saves system cost, while the LP crystal option saves power. © 2006 Microchip Technology Inc. dsPIC30F1010/202X 18.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...

Page 200

... Primary Oscillator Clock Stability Detector Switching and Control Block Oscillator Start-up Timer Internal Low-Power RC Oscillator (LPRC) Fail-Safe Clock FCKSM<1:0> Monitor (FSCM) 2 Preliminary Oscillator Configuration Bits PWRSAV Instruction Wake-up Request COSC<2:0> NOSC<2:0> OSWEN System Clock Oscillator Trap © 2006 Microchip Technology Inc. ...

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