DSPIC30F2020-30I/MM Microchip Technology, DSPIC30F2020-30I/MM Datasheet - Page 188

• Manufacturer Part Number: DSPIC30F2020-30I/MM
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020-30I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 15MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

dsPIC30F1010/202X
16.17 A/D Sample and Convert Timing
The sample and hold circuits assigned to the input pins
have their own timing logic that is triggered when an
external sample and convert request (from PWM or
TMR) is made. The sample and hold circuits have a
fixed two clock data sample period. When the sample
has been acquired, then the ADC control logic is noti-
FIGURE 16-3:
DS70178C-page 186
adc_clk
sample_even
sample_odd
connect_first
connect_second
convert_en
capture_first_data
capture_second_data
state counter
0
1
10th 9th 8th
2
DETAILED CONVERSION SEQUENCE TIMINGS, SEQSAMP = 0, NOT BUSY
3
4
T
7th
AD
5
6th
6
5th
7
4th
8
3rd 2nd 1st
9
Preliminary
10
11
10th 9th 8th
fied of a pending request, then the conversion is
performed as the conversion resources become
available.
The ADC module always converts pairs of analog input
channels, so a typical conversion process requires 24
clock cycles.
12
13
14
15
7th
16
6th
17
5th
© 2006 Microchip Technology Inc.
18
4th
19
3rd
20
2nd 1st
21
0
1
2