DSPIC30F2020-30I/MM Microchip Technology, DSPIC30F2020-30I/MM Datasheet - Page 185

• Manufacturer Part Number: DSPIC30F2020-30I/MM
• Description: IC DSPIC MCU/DSP 12K 28QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020-30I/MM

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-QFN
• Core Frequency: 15MHz
• Core Supply Voltage: 3.3V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 21
• Flash Memory Size: 12KB
• Supply Voltage Range: 3V To 3.6V
• Package: 28QFN-S EP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.9
The ADC module also provides individual interrupts
outputs for each analog input pair. These interrupts are
always enabled within the module. The pair interrupts
can be individually enabled or disabled via the
associated interrupt enable bits in the IEC registers.
Using the group interrupts may require the interrupt
service routine to determine which interrupt source
generated the interrupt. For applications that use sep-
arate software tasks to process ADC data, a common
interrupt vector can cause performance bottlenecks.
The use of the individual pair interrupts can save many
clock cycles compared to using the group interrupt to
process multiple interrupt sources. The individual pair
interrupts support the construction of application
software that is responsive and organized on a task
basis.
Regardless of whether an individual pair interrupt or the
global interrupt are used to respond to an interrupt
request from an ADC conversion, the PxRDY bits in the
ADSTAT register function in the same manner.
The use of the individual pair interrupts also enables
the user to change the interrupt priority of individual
ADC channels (pairs) as compared to the fixed priority
structure of the group interrupt.
NOTE: The use of individual interrupts DOES NOT
affect the priority structure of the ADC with respect
to the order of input pair conversion.
The use of individual interrupts can reduce the problem
of accidently “losing” a pending interrupt while
processing and clearing a current interrupt
16.10 Early Interrupt Generation
The EIE control bit in the ADCON register enables the
generation of the interrupts after completion of the first
conversion instead of waiting for the completion of both
inputs of an input pair. Even though the second input
will still be in the conversion process, the software can
be written to perform some of the computations using
the first data value while the second conversion is
completed.
The user software can be written to account for the 500
nsec conversion period of the second input before
using the second data, or the user can poll the PEND
bit in the ADCPCx register.
The PEND bit remains set until both conversions of a
pair have been completed. The PxRDY bit for the asso-
ciated interrupt is set in the ADSTAT register at the
completion of the first conversion, and remains set until
it is cleared by the user.
© 2006 Microchip Technology Inc.
Individual Pair Interrupts
Preliminary
16.11 Conflict Resolution
If more than one conversion pair request is active at the
same time, the ADC control logic processes the
requests in a top-down manner, starting at analog pair
#0 (AN1/AN0) and ending at analog pair #5 (AN11/
AN10). This is not a “round-robin” process.
16.12 Deliberate Conflicts
If the user specifies the same conversion trigger source
for multiple “conversion pairs”, then the ADC module
functions like other dsPIC30F ADC modules; i.e., it pro-
cesses the requested conversions sequentially (in
pairs) until the sequence has been completed.
16.13 ADC Clock Selection
The ADCS<2:0> bits in the ADCON register specify the
clock divisor value for the ADC clock generation logic.
The input to the ADC clock divisor is the system clock
(240 MHz @ 30 MIPS) when the PLL is operating. This
high-frequency clock provides the needed timing reso-
lution to generate a 24 MHz ADC clock signal required
to process two ADC conversions in 1 microsecond.
16.14 ADC Base Register
It is expected that the user application may have the
ADC module generate 500,000 interrupts per second.
To speed the evaluation of the PxRDY bits in the
ADSTAT register, the ADC module features the read/
write register: ADBASE. When read, the ADBASE reg-
ister provides a sum of the contents of the ADBASE
register plus an encoding of the PxRDY bits set in the
ADSTAT register.
The Least Significant bit of the ADBASE register is
forced to zero, which ensures that all (ADBASE +
PxRDY) results are on instruction boundaries.
The PxRDY bits are binary priority encoded; P0RDY is
the highest priority and P5RDY is the lowest priority.
The encoded priority result is shifted left two bit posi-
tions and added to the contents of the ADBASE regis-
ter. Thus the priority encoding yields addresses that
are on two instruction word boundaries.
The user will typically load the ADBASE register with
the base address of a “Jump” table that contains either
the addresses of the appropriate ISRs or branches to
the appropriate ISR. The encoded PxRDY values are
set up to reserve two instruction words per entry in the
Jump table. It is expected that the user software will
use one instruction word to load an identifier into a W
register, and the other instruction will be a branch to
the appropriate ISR.
Note:
dsPIC30F1010/202X
The ADC module will NOT repeatedly loop
once triggered. Each sequence of
conversions requires a trigger or multiple
triggers.
DS70178C-page 183