DSPIC30F2020-30I/MMB32 Microchip Technology, DSPIC30F2020-30I/MMB32 Datasheet - Page 35
![IC DSPIC MCU/DSP 12K 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
DSPIC30F2020-30I/MMB32
Manufacturer Part Number
DSPIC30F2020-30I/MMB32
Description
IC DSPIC MCU/DSP 12K 28QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DSPIC30F2011-20IP.pdf
(26 pages)
3.DSPIC30F1010-30ISO.pdf
(26 pages)
4.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2020-30I/MMB32
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
Q4035438A
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2020-30I/MMB32
Manufacturer:
Microchip Technology
Quantity:
135
- AC164335 PDF datasheet
- DSPIC30F2011-20IP PDF datasheet #2
- DSPIC30F1010-30ISO PDF datasheet #3
- DSPIC30F1010-30ISO PDF datasheet #4
- Current page: 35 of 286
- Download datasheet (5Mb)
FIGURE 3-5:
3.2
The core has two data spaces. The data spaces can be
considered either separate (for some DSP instruc-
tions), or as one unified linear address range (for MCU
instructions). The data spaces are accessed using two
Address Generation Units (AGUs) and separate data
paths.
3.2.1
The data space memory is split into two blocks, X and
Y data space. A key element of this architecture is that
Y space is a subset of X space, and is fully contained
within X space. In order to provide an apparent linear
addressing space, X and Y spaces have contiguous
addresses.
© 2006 Microchip Technology Inc.
Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address
BSET
MOV
MOV
MOV
Space
Data
EA
Upper half of Data
Space is mapped
into Program Space
(i.e., it defines the page in program space to which the upper half of data space is being mapped).
Data Address Space
CORCON,#2
#0x00, W0
W0, PSVPAG
0x9200, W0
DATA SPACE MEMORY MAP
16
EA<15> = 0
EA<15> = 1
DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION
15
15
; PSV bit set
; Set PSVPAG register
; Access program memory location
; using a data space access
Data Space
0x8000
15
0xFFFF
0x0000
Preliminary
Concatenation
Address
PSVPAG
0x00
When executing any instruction other than one of the
MAC class of instructions, the X block consists of the
256 byte data address space (including all Y
addresses). When executing one of the MAC class of
instructions, the X block consists of the 256 bytes data
address space excluding the Y address block (for data
reads only). In other words, all other instructions regard
the entire data memory as one composite address
space. The MAC class instructions extract the Y
address space from data space and address it using
EAs sourced from W10 and W11. The remaining X data
space is addressed using W8 and W9. Both address
spaces are concurrently accessed only with the MAC
class instructions.
A data space memory map is shown in Figure 3-6.
8
dsPIC30F1010/202X
(1)
23
23
Program Space
15
Data Read
DS70178C-page 33
0
0x001FFE
0x100100
0x001200
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