ATMEGA644P-20PQ Atmel, ATMEGA644P-20PQ Datasheet - Page 255

• Manufacturer Part Number: ATMEGA644P-20PQ
• Description: MCU AVR 64K FLASH 20MHZ 40-PDIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644P-20PQ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.9
20.9.1
8011O–AVR–07/10
Register Description
ADMUX – ADC Multiplexer Selection Register
Example:
ADMUX = 0xED (ADC3 - ADC2, 10× gain, 2.56V reference, left adjusted result)
Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV.
ADCR = 512 × 10 × (300 - 500) / 2560 = -400 = 0x270
ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the
result: ADCL = 0x70, ADCH = 0x02.
• Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
Table 20-3.
Note:
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see
page
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
The value of these bits selects which combination of analog inputs are connected to the ADC.
These bits also select the gain for the differential channels. See
details. If these bits are changed during a conversion, the change will not go in effect until this
conversion is complete (ADIF in ADCSRA is set).
Bit
(0x7C)
Read/Write
Initial Value
REFS1
0
0
1
1
258.
If 10× og 200× gain is selected, only 2.56V should be used as Internal Voltage Reference.
REFS0
Voltage Reference Selections for ADC
REFS1
0
1
0
1
R/W
7
0
Voltage Reference Selection
AREF, Internal Vref turned off
AVCC with external capacitor at AREF pin
Internal 1.1V Voltage Reference with external capacitor at AREF pin
Internal 2.56V Voltage Reference with external capacitor at AREF pin
REFS0
R/W
6
0
ADLAR
R/W
5
0
MUX4
R/W
4
0
”ADCL and ADCH – The ADC Data Register” on
ATmega164P/324P/644P
MUX3
R/W
3
0
MUX2
R/W
2
0
Table 20-4 on page 256
Table
MUX1
R/W
1
0
20-3. If these bits are
MUX0
R/W
0
0
ADMUX
255
for