ATMEGA32HVB-8X3 Atmel, ATMEGA32HVB-8X3 Datasheet - Page 94
![MCU AVR 32KB FLASH 8MHZ 44TSSOP](/photos/12/32/123222/44x1-tssop_sml.jpg)
ATMEGA32HVB-8X3
Manufacturer Part Number
ATMEGA32HVB-8X3
Description
MCU AVR 32KB FLASH 8MHZ 44TSSOP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32HVB-8X3
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI
Peripherals
POR, WDT
Number Of I /o
17
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 25 V
Data Converters
A/D 7x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TSSOP
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, TWI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
17
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRSB200
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 7 Channel
Package
44TSSOP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
5|9|12|15|18|24 V
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA32HVB-8X3
Manufacturer:
Atmel
Quantity:
408
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17.10 Register Description
17.10.1
8042B–AVR–06/10
TCCRnA – Timer/Counter n Control Register A
• Bit 7 – TCWn: Timer/Counter Width
When this bit is written to one 16-bit mode is selected. Timer/Counter n width is set to 16-bits
and the Output Compare Registers OCRnA and OCRnB are combined to form one 16-bit Output
Compare Register. Because the 16-bit registers TCNTnH/L and OCRnB/A are accessed by the
AVR CPU via the 8-bit data bus, special procedures must be followed. These procedures are
described in section
• Bit 6 – ICENn: Input Capture Mode Enable
The Input Capture Mode is enabled when this bit is written to one.
• Bit 5 – ICNCn: Input Capture Noise Canceler
Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is acti-
vated, the input from the Input Capture Source is filtered. The filter function requires four
successive equal valued samples of the Input Capture Source for changing its output. The Input
Capture is therefore delayed by four System Clock cycles when the noise canceler is enabled.
• Bit 4 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Source that is used to trigger a capture event.
When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the
ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is trig-
gered according to the ICESn setting, the counter value is copied into the Input Capture
Register. The event will also set the Input Capture Flag (ICFn), and this can be used to cause an
Input Capture Interrupt, if this interrupt is enabled.
• Bit 3 – ICSn: Input Capture Select
When written logic one, this bit enables the input capture function in Timer/Counter n to be trig-
gered by the alternative Input Capture Source. To make the comparator trigger the
Timer/Counter n Input Capture interrupt, the TICIEn bit in the Timer Interrupt Mask Register
(TIMSK) must be set. See
• Bits 2:1 – Reserved
These bits are reserved in the ATmega16HVB/32HVB and will always read as zero.
• Bit 0 – WGMn0: Waveform Generation Mode
This bit controls the counting sequence of the counter, the source for maximum (TOP) counter
value, see
Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see
Timing Diagrams” on page
Bit
0x24 (0x44)
Read/Write
Initial Value
Figure 17-6 on page
TCWn
R/W
7
0
”Accessing Registers in 16-bit Mode” on page
ICENn
R/W
6
0
Table 17-3 on page 88
89).
89. Modes of operation supported by the Timer/Counter unit are:
ICNCn
R/W
5
0
ICESn
R/W
4
0
and
ATmega16HVB/32HVB
ICSn
R/W
3
0
Table 17-4 on page
R
2
–
0
90.
R
1
–
0
88.
WGMn0
R/W
”Timer/Counter
0
0
TCCRnA
94
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