ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 135

• Manufacturer Part Number: ATMEGA162V-8PU
• Description: IC AVR MCU 16K 8MHZ 1.8V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Extended
Timer/Counter
Interrupt Mask
Register – ETIMSK
Timer/Counter
Interrupt Flag Register
– TIFR
2513K–AVR–07/09
(1)
(1)
Interrupt Vector
TIFR, is set.
• Bit 3 – TICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
Note:
• Bit 5 – TICIE3: Timer/Counter3, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 4 – OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 3 – OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector
TIFR, is set.
• Bit 2 – TOIE3: Timer/Counter3, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter3 overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Interrupts” on page
Note:
• Bit 7 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOV1 Flag is set when the timer overflows. Refer to
behavior when using another WGMn3:0 bit setting.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
(See “Interrupts” on page
1. This register contains interrupt control bits for several Timer/Counters, but only Timer3 bits are
1. This register contains flag bits for several Timer/Counters, but only Timer1 bits are described
described in this section. The remaining bits are described in their respective Timer sections.
in this section. The remaining bits are described in their respective Timer sections.
TOV1
R/W
R
7
0
7
0
(See “Interrupts” on page
(See “Interrupts” on page
(See “Interrupts” on page
OCF1A
R/W
6
R
0
6
0
57.) is executed when the TOV3 Flag, located in TIFR, is set.
TICIE3
OC1FB
R/W
R/W
5
0
5
0
57.) is executed when the ICF1 Flag, located in TIFR, is set.
57.) is executed when the ICF3 Flag, located in TIFR, is set.
OCIE3A
OCF2
R/W
R/W
4
0
4
0
57.) is executed when the OCF1B Flag, located in
57.) is executed when the OCF3A Flag, located in
57.) is executed when the OCF3B Flag, located in
OCIE3B
ICF1
R/W
R/W
3
0
3
0
TOV2
Table 56 on page 130
R/W
TOIE3
R/W
2
0
2
0
TOV0
R/W
1
0
R
1
–
0
ATmega162/V
OCF0
R/W
0
0
R
0
–
0
for the TOV1 Flag
ETIMSK
TIFR
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