ATMEGA162V-8PU Atmel, ATMEGA162V-8PU Datasheet - Page 74

• Manufacturer Part Number: ATMEGA162V-8PU
• Description: IC AVR MCU 16K 8MHZ 1.8V 40DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA162V-8PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: JTAG/SPI/USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Package: 40PDIP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

74
ATmega162/V
Table 33. Overriding Signals for Alternate Functions in PB7..PB4
Table 34. Overriding Signals for Alternate Functions in PB3..PB0
Notes:
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
1. CKOUT is one if the CKOUT Fuse is programmed.
2. clk
I/O
PB7/SCK
SPE • MSTR
PORTB7 •
PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
0
0
SCK INPUT
–
is the divided system clock.
PB3/AIN1/TXD1
TXEN1
0
TXEN1
1
TXEN1
TXD1
0
0
–
AIN1 INPUT
PB6/MISO
SPE • MSTR
PORTB6 • PUD
SPE • MSTR
0
SPI SLAVE
OUTPUT
0
0
SPI MSTR INPUT
–
SPE • MSTR
PB2/AIN0/RXD1
AIN0 INPUT
RXEN1
PORTB2• PUD
RXEN1
0
0
0
0
0
RXD1
PB5/MOSI
SPE • MSTR
PORTB5 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR
OUTPUT
0
0
SPI SLAVE INPUT
–
PB1/T1/OC2
0
0
0
0
OC2 ENABLE
OC2
0
0
T1 INPUT
–
PB0/T0/OC0
0
0
CKOUT
1
CKOUT + OC0
ENABLE
if (CKOUT) then
else
0
0
T0 INPUT
–
PB4/SS/OC3B
SPE • MSTR
PORTB4 •
PUD
SPE • MSTR
0
OC3B
ENABLE
OC3B
0
0
SPI SS
–
clk
OC0
I/O
(1)
(2)
2513K–AVR–07/09